MB84VD2118XEM-70 Datasheet, PDF (48/52 Pages) SPANSION – Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS

MB84VD2118XEM/2119XEM-70
2. Data Retention Characteristics (SRAM)
Parameter
Symbol
Data Retention Supply Voltage
VDH
Standby Current
VDH = 1.5 V
IDDS2
Chip Deselect to Data Retention Mode Time
tCDR
Recovery Time
tR
Note : tRC: Read cycle time
• CE1s Controlled Data Retention Mode *¹
VCCs
DATA RETENTION MODE
2.7 V
Value
Min Typ Max
1.5
—
3.3
—
3
10
0
—
—
tRC
—
—
Unit
V
µA
ns
ns
*2
*2
VIH
VDH
VCCS –0.2 V
CE1s
tCDR
tR
GND
*1 : In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs–0.2 V or Vss
to 0.2 V during data retention mode. Other input and input/output pins can be used between –0.3 V to
Vccs+0.3 V.
*2 : When CE1s is operating at the VIH Min level (2.2 V), the standby current is given by ISB1s during the
transition of VCCs from 3.3 V to 2.2 V.
• CE2s Controlled Data Retention Mode *
VCCs
DATA RETENTION MODE
2.7 V
VDH
VIH
CE2s
tCDR
tR
VIL
0.2 V
GND
* : In CE2s controlled data retention mode, input and input/output pins can be used between
–0.3 V to Vccs+0.3 V.
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