COM20022I-3.3V Datasheet, PDF (69/73 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Chapter 9 Appendix A
This appendix describes the function of the NOSYNC and EF bits.
9.1
NOSYNC Bit
The NOSYNC bit controls whether or not the RAM initialization sequence requires the line to be idle by
enabling or disabling the SYNC command during initialization. It is defined as follows:
NOSYNC: Enable/Disable SYNC command during initialization. NOSYNC=0, Enable (Default): the line
has to be idle for the RAM initialization sequence to be written, NOSYNC=1, Disable: the line does not
have to be idle for the RAM initialization sequence to be written.
The following discussion describes the function of this bit:
During initialization, after the CPU writes the Node ID, the COM20022I 3V will write "D1"h data to Address
000h and Node-ID to Address 001h of its internal RAM within 3uS. These values are read as part of the
diagnostic test. If the D1 and Node-ID initialization sequence cannot be read, the initialization routine will
report it as a device diagnostic failure. These writes are controlled by a micro-program which sometimes
waits if the line is active; SYNC is the micro-program command that causes the wait. When the micro-
program waits, the initial RAM write does not occur, which causes the diagnostic error. Thus in this case,
if the line is not idle, the initialization sequence may not be written, which will be reported as a device
diagnostic failure.
However, the initialization sequence and diagnostics of the COM20022I 3V should be independent of the
network status. This is accomplished through some additional logic to decode the program counter,
enabled by the NOSYNC bit. When it finds that the micro-program is in the initialization routine, it disables
the SYNC command. In this case, the initialization will not be held up by the line status.
Thus, by setting the NOSYNC bit, the line does not have to be idle for the RAM initialization sequence to
be written.
9.2
EF Bit
The EF bit controls several modifications to internal operation timing and logic. It is defined as follows:
EF: Enable/Disable the new internal operation timing and logic refinements. EF=0: (Default) Disable the
new internal operation timing (the timing is the same as in the COM20020 Rev. B); EF=1: Enable the new
internal operation timing.
The EF bit controls the following timing/logic refinements in the COM20022I 3V:
a) Extend Interrupt Disable Time
While the interrupt is active (nINTR pin=0), the interrupt is disabled by writing the Clear Tx/Rx interrupt
and Clear Flag command and by reading the Next-ID register. This minimum disable time is changed
by the Data Rate. For example, it is 200nS at 2.5Mbps and 50nS at 10Mbps. The 50nS width will be
too short to for the Interrupt to be seen.
Setting the EF bit will change the minimum disable time to always be more than 200nS even if the
Data Rate is 10Mbps . This is done by changing the clock which is supplied to the Interrupt Disable
logic. The frequency of this clock is always 20MHz even if the data rate is 10Mbps.
SMSC COM20022I 3.3V Rev.C
Page 69
DATASHEET
Revision 03-08-07