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COM20022I-3.3V Datasheet, PDF (34/73 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Table 6.10 - Sub Address Register
BIT
7-3
2,1,0
BIT NAME
Reserved
Sub Address 2,1,0
SYMBOL
SUBAD
2,1,0
DESCRIPTION
These bits are undefined. They must be 0.
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD2 SUBAD1 SUBAD0 Register
0
0
0
Tentative ID \ (Same
0
0
1
Node ID \ as in
0
1
0
Setup 1 / Config
0
1
1
Next ID
/ Register)
1
0
0
Setup 2
1
0
1
Bus Control
1
1
0
Reserved
1
1
1
Reserved
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by
writing the Configuration Register.
BIT
BIT NAME
7 Reset
6 Command
Chaining Enable
5 Transmit Enable
Table 6.11 - Configuration Register
SYMBOL
RESET
CCHEN
TXEN
DESCRIPTION
A software reset of the COM20022I 3V is executed by
writing a logic "1" to this bit. A software reset does not
reset the microcontroller interface mode, nor does it affect
the Configuration Register. The only registers that the
software reset affect are the Status Register, the Next ID
Register, and the Diagnostic Status Register. This bit
must be brought back to logic "0" to release the reset.
This bit, if high, enables the Command Chaining operation
of the device. Please refer to the Command Chaining
section for further details. A low level on this bit ensures
software compatibility with previous SMSC ARCNET
devices.
When low, this bit disables transmissions by keeping
nPULSE1, nPULSE2 if in non-Backplane Mode, and
nTXEN pin inactive. When high, it enables the above
signals to be activated during transmissions. This bit
defaults low upon reset. This bit is typically enabled once
the Node ID is determined, and never disabled during
normal operation. Please refer to the Improved
Diagnostics section for details on evaluating network
activity.
Revision 03-08-07
Page 34
DATASHEET
SMSC COM20022I 3.3V Rev.C