COM20022I-3.3V Datasheet, PDF (25/73 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Chapter 6 Functional Description
6.1
Microsequencer
The COM20022I 3V contains an internal microsequencer which performs all of the control operations
necessary to carry out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program
counter, two instruction registers, an instruction decoder, a no-op generator, jump logic, and
reconfiguration logic.
The COM20022I 3V derives a 20 MHz and a 10 MHz clock from the output clock of the Clock Multiplier.
These clocks provide the rate at which the instructions are executed within the COM20022I 3V. The 20
MHz clock is the rate at which the program counter operates, while the 10 MHz clock is the rate at which
the instructions are executed. The microprogram is stored in the ROM and the instructions are fetched
and then placed into the instruction registers. One register holds the opcode, while the other holds the
immediate data. Once the instruction is fetched, it is decoded by the internal instruction decoder, at which
point the COM20022I 3V proceeds to execute the instruction. When a no-op instruction is encountered,
the microsequencer enters a timed loop and the program counter is temporarily stopped until the loop is
complete. When a jump instruction is encountered, the program counter is loaded with the jump address
from the ROM. The COM20022I 3V contains an internal reconfiguration timer which interrupts the
microsequencer if it has timed out. At this point the program counter is cleared and the MYRECON bit of
the Diagnostic Status Register is set.
REGISTER
STATUS
DIAG.
STATUS
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA
*See Table 6.2
SUB ADR
CONFIG-
URATION
TENTID
NODE ID
SETUP1
NEXT ID
SETUP2
MSB
RI/TRI
MY-
RECON
RD-DATA
A7
D7
(R/W)
(Note 6.1)
RESET
TID7
NID7
P1 MODE
NXT ID7
RBUS-
TMG
X/RI
DUPID
AUTO-INC
A6
D6
(R/W)
(Note 6.1)
CCHEN
TID6
NID6
FOUR
NAKS
NXT ID6
X
Table 6.1 - Read Register Summary
READ
X/TA
POR
TEST
RECON
RCV-ACT TOKEN EXC-NAK TENTID
X
X
X
A10
A5
A4
A3
A2
D5
D4
D3
D2
X
X
X
SUB-AD2
TXEN
TID5
NID5
X
ET1
TID4
NID4
RCV- ALL
ET2
TID3
NID3
CKP3
BACK-
PLANE
TID2
NID2
CKP2
NXT ID5
CKUP1
NXT ID4
CKUP0
NXT ID3
EF
NXT
ID2
NO-SYNC
TMA
NEW
NEXTID
A9
A1
D1
SUB-AD1
SUB-AD1
TID1
NID1
CKP1
NXT ID1
RCN-TM1
LSB
TA/
TTA
X
A8
A0/ SWAP
D0
SUB-AD0
SUB-AD0
TID0
NID0
SLOW-
ARB
NXT ID0
RCM-TM2
ADDR
00
01
02
03
04
05
06
07-0
07-1
07-2
07-3
07-4
SMSC COM20022I 3.3V Rev.C
Page 25
DATASHEET
Revision 03-08-07