COM20022I-3.3V Datasheet, PDF (20/73 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
A2-A0, nCS
nRD
Delayed nRD
(nRD1)
Sampled A2-A0, nCS
More delayed nRD
(nRD2)
VALID
VALID
Figure 5.3 - High Speed CPU Bus Timing – Intel CPU Mode
The I/O address and Chip Select signals, which are supplied to the data output logic, are not sampled.
Also, the nRD signal is not delayed, because the above sampling and delaying paths decrease the data
access time of the read cycle.
The above sampling and delaying signals are supplied to the Read Pulse Generation logic which
generates the clearing pulse for the Diagnostic register and generates the starting pulse of the RAM
Arbitration. Typical delay time between nRD and nRD1 is around 15nS and between nRD1 and nRD2 is
around 10nS.
Longer pulse widths are needed due to these delays on nRD signal. However, the CPU can insert some
wait cycles to extend the width without any impact on performance.
The BUSTMG pin is used to support this function. It is used to Enable/Disable the High Speed CPU Read
and Write function. It is defined as: BUSTMG = 0, the High Speed CPU Read and Write operations are
enabled; BUSTMG = 1, the High Speed CPU Read and Write operations are disabled if the RBUSTMG bit
is 0. If BUSTMG = 1 and RBUSTMG = 1, High Speed CPU Read operations are enabled (see definition of
RBUSTMG bit below).
The RBUSTMG bit was added to Disable/Enable the High Speed CPU Read function. It is defined as:
RBUSTMG=0, Disabled (Default); RBUSTMG=1, Enabled.
In the MOTOROLA CPU mode (DIR, nDS mode), the same modifications apply.
BUSTMG PIN
0
1
1
RBUSTMG BIT
X
0
1
BUS TIMING MODE
High Speed CPU Read and Write
Normal Speed CPU Read and Write
High Speed CPU Read and Normal Speed CPU Write
Revision 03-08-07
Page 20
DATASHEET
SMSC COM20022I 3.3V Rev.C