COM20022I-3.3V Datasheet, PDF (30/73 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
in the table following are limited by a maximum number of nodes in the network. These time-out period
values are for 10Mbps. For other data rates, scale the time-out period time values accordingly; the
maximum node count remains the same.
Note 6.3
RCNTM1
0
0
1
1
RCNTM0
0
1
0
1
TIME-OUT PERIOD
210 mS
52.5 mS
26.25 mS
13.125 mS (Note 6.3)
MAX NODE COUNT
Up to 255 nodes
Up to 64 nodes
Up to 32 nodes
Up to 16 nodes (Note 6.3)
The node ID value 255 must exist in the network for the 13.125 mS time-out to be valid.
6.2.14 Bus Control Register
The W16 bit is used to enable/disable the 16 bit access.
Table 6.5 - Status Register
BIT BIT NAME SYMBOL
DESCRIPTION
7 Receiver
Inhibited
RI
This bit, if high, indicates that the receiver is not enabled because
either an "Enable Receive to Page fnn" command was never
issued, or a packet has been deposited into the RAM buffer page
fnn as specified by the last "Enable Receive to Page fnn"
command. No messages will be received until this command is
issued, and once the message has been received, the RI bit is
set, thereby inhibiting the receiver. The RI bit is cleared by
issuing an "Enable Receive to Page fnn" command. This bit,
when set, will cause an interrupt if the corresponding bit of the
Interrupt Mask Register (IMR) is also set. When this bit is set and
another station attempts to send a packet to this station, this
station will send a NAK.
6,5 (Reserved)
These bits are undefined.
4 Power On Reset POR
This bit, if high, indicates that the COM20022I 3V has been reset
by either a software reset, a hardware reset, or writing 00H to the
Node ID Register. The POR bit is cleared by the "Clear Flags"
command.
3 Test
TEST
This bit is intended for test and diagnostic purposes. It is a logic
"0" under normal operating conditions.
2 Reconfiguration RECON This bit, if high, indicates that the Line Idle Timer has timed out
because the RXIN pin was idle for 20.5 S. The RECON bit is
cleared during a "Clear Flags" command. This bit, when set, will
cause an interrupt if the corresponding bit in the IMR is also set.
The interrupt service routine should consist of examining the
MYRECON bit of the Diagnostic Status Register to determine
whether there are consecutive reconfigurations caused by this
node.
1 Transmitter
Message
Acknowledged
TMA
This bit, if high, indicates that the packet transmitted as a result of
an "Enable Transmit from Page fnn" command has been
acknowledged. This bit should only be considered valid after the
TA bit (bit 0) is set. Broadcast messages are never
acknowledged. The TMA bit is cleared by issuing the "Enable
Transmit from Page fnn" command.
Revision 03-08-07
Page 30
DATASHEET
SMSC COM20022I 3.3V Rev.C