COM20022I-3.3V Datasheet, PDF (28/73 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
6.2.4 Node ID Register
The Node ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up
accordingly (please refer to the Configuration Register and SUB ADR Register). The Node ID Register
contains the unique value which identifies this particular node. Each node on the network must have a
unique Node ID value at all times. The Duplicate ID bit of the Diagnostic Status Register helps the user
find a unique Node ID. Refer to the Initialization Sequence section for further detail on the use of the
DUPID bit. The core of the COM20022I 3V does not wake up until a Node ID other than zero is written
into the Node ID Register. During this time, no microcode is executed, no tokens are passed by this node,
and no reconfigurations are caused by this node. Once a non-zero NodeID is placed into the Node ID
Register, the core wakes up but will not join the network until the TXEN bit of the Configuration Register is
set. While the Transmitter is disabled, the Receiver portion of the device is still functional and will provide
the user with useful information about the network. The Node ID Register defaults to the value 0000 0000
upon hardware reset only.
6.2.5 Next ID Register
The Next ID Register is an 8-bit, read-only register, accessed when the sub-address bits are set up
accordingly (please refer to the Configuration Register and SUB ADR Register). The Next ID Register
holds the value of the Node ID to which the COM20022I 3V will pass the token. When used in conjunction
with the Tentative ID Register, the Next ID Register can provide a complete network map. The Next ID
Register is updated each time a node enters/leaves the network or when a network reconfiguration occurs.
Each time the microsequencer updates the Next ID Register, a New Next ID interrupt is generated. This bit
is cleared by reading the Next ID Register. Default value is 0000 0000 upon hardware or software reset.
6.2.6 Status Register
The COM20022I 3V Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6,
are software compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the
Extended Timeout status was provided in bits 5 and 6 of the Status Register. In the COM20022I 3V, the
COM20020, the COM90C66, and the COM90C165, COM20020-5, COM20051 and COM20051+ these
bits exist in and are controlled by the Configuration Register. The Status Register contents are defined as
in Table 6.5, but are defined differently during the Command Chaining operation. Please refer to the
Command Chaining section for the definition of the Status Register during Command Chaining operation.
The Status Register defaults to the value 1XX1 0001 upon either hardware or software reset.
6.2.7 Diagnostic Status Register
The Diagnostic Status Register contains seven read-only bits which help the user troubleshoot the network
or node operation. Various combinations of these bits and the TXEN bit of the Configuration Register
represent different situations. All of these bits, except the Excessive NACK bit and the New Next ID bit,
are reset to logic "0" upon reading the Diagnostic Status Register or upon software or hardware reset. The
EXCNAK bit is reset by the "POR Clear Flags" command or upon software or hardware reset. The
Diagnostic Status Register defaults to the value 0000 000X upon either hardware or software reset.
6.2.8 Command Register
Execution of commands are initiated by performing microcontroller writes to this register. Any
combinations of written data other than those listed in Table 6.7 are not permitted and may result in
incorrect chip and/or network operation.
Revision 03-08-07
Page 28
DATASHEET
SMSC COM20022I 3.3V Rev.C