COM20022I-3.3V Datasheet, PDF (40/73 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
next byte of data into the data register, again to be read by the microcontroller. This process is continued
until the entire packet is read out of RAM. Refer to Figure 6.1Error! Reference source not found. for an
illustration of the Sequential Access operation. When switching between reads and writes, the pointer
must first be written with the starting address. At least one cycle time should separate the pointer being
loaded and the first read (see timing parameters).
6.3.2 Access Speed
The COM20022I 3V is able to accommodate very fast access cycles to its registers and buffers. Arbitration
to the buffer does not slow down the cycle because the pointer based access method allows data to be
prefetched from memory and stored in a temporary register. Likewise, data to be written is stored in the
temporary register and then written to memory.
For systems which do not require quick access time, the arbitration clock may be slowed down by setting
bit 0 of the Setup1 Register equal to logic "1". Since the Slow Arbitration feature divides the input clock by
two, the duty cycle of the input clock may be relaxed.
6.3.3 Software Interface
The microcontroller interfaces to the COM20022I 3V via software by accessing the various registers.
These actions are described in the Internal Registers section. The software flow for accessing the data
buffer is based on the Sequential Access scheme. The basic sequence is as follows:
ƒ Disable Interrupts
ƒ Write to Pointer Register High (specifying Auto-Increment mode)
ƒ Write to Pointer Register Low (this loads the address)
ƒ Enable Interrupts
ƒ Read or Write the Data Register (repeat as many times as necessary to empty or fill the buffer)
ƒ The pointer may now be read to determine how many transfers were completed.
The software flow for controlling the Configuration, Node ID, Tentative ID, and Next ID registers is
generally limited to the initialization sequence and the maintenance of the network map.
Additionally, it is necessary to understand the details of how the other Internal Registers are used in the
transmit and receive sequences and to know how the internal RAM buffer is properly set up. The
sequence of events that tie these actions together is discussed as follows.
6.3.4 Selecting RAM Page Size
During normal operation, the 2K x 8 of RAM is divided into four pages of 512 bytes each. The page to be
used is specified in the "Enable Transmit (Receive) from (to) Page fnn" command, where "nn" specifies
page 0, 1, 2, or 3. This allows the user to have constant control over the allocation of RAM.
When the Offset bit "f" (bit 5 of the "Enable Transmit (Receive) from (to) Page fnn" command word) is set
to logic "1", an offset of 256 bytes is added to the page specified. For example: to transmit from the second
half of page 0, the command "Enable Transmit from Page fnn" (fnn=100 in this case) is issued by writing
0010 0011 to the Command Register. This allows a finer resolution of the buffer pages without affecting
software compatibility. This scheme is useful for applications which frequently use packet sizes of 256
bytes or less, especially for microcontroller systems with limited memory capacity. The remaining portions
of the buffer pages which are not allocated for current transmit or receive packets may be used as
temporary storage for previous network data, packets to be sent later, or as extra memory for the system,
which may be indirectly accessed.
Revision 03-08-07
Page 40
DATASHEET
SMSC COM20022I 3.3V Rev.C