COM20022I-3.3V Datasheet, PDF (33/73 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
BIT
BIT NAME
7 Read Data
6 Auto Increment
5-4 (Reserved)
3 (Reserved)
2-0 Address 10-8
Table 6.8 - Address Pointer High Register
SYMBOL
RDDATA
AUTOINC
A10-A8
DESCRIPTION
This bit tells the COM20022I 3V whether the following
access will be a read or write. A logic "1" prepares the
device for a read, a logic "0" prepares it for a write.
This bit controls whether the address pointer will
increment automatically after DATA register access. A
logic "1" on this bit allows automatic increment of the
pointer after each DATA register access, while a logic "0"
disables this function.
- At 8 bit access mode (W16=0)
AUTOINC=0: The address pointer does not increment
AUTOINC=1: The address pointer increment (+1)
- At 16 bit access mode (W16=1)
AUTOINC=0: The address pointer does not increment
AUTOINC=1: The address pointer increment (+2)
Please refer to the Sequential Access Memory section for
further detail.
These bits are undefined. They must be 0.
This bit must be “0” for normal operation.
These bits hold the upper three address bits which
provide addresses to RAM.
BIT
BIT NAME
7-0 Address 7-0
Table 6.9 - Address Pointer Low Register
SYMBOL
A7-A0
SWAP
DESCRIPTION
These bits hold the lower 8 address bits which provide the
addresses to RAM.
When 16 bit access is enabled, (W16=1), A0 becomes the
SWAP bit. Swap bit is undefined after a hardware reset.
The swap bit must be set before W16 bit is set to “1”. The
swap bit is used to swap the upper and lower data byte.
The swap bit influences CPU cycle. See Table Below.
Detected Host
Interface Mode
Intel 80xx Mode
(RD, WR Mode)
Motorola 68xx Mode
(DIR, DS Mode)
Swap Bit
0
1
0
1
D15-D8
Pin
Odd
Even
Even
Odd
D7-D0
Pin
Even
Odd
Odd
Even
SMSC COM20022I 3.3V Rev.C
Page 33
DATASHEET
Revision 03-08-07