COM20022I-3.3V Datasheet, PDF (5/73 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
LIST OF FIGURES
Figure 3.1 - COM20022I 3V Operation ........................................................................................................................10
Figure 5.1 - Multiplexed, 8051 - Like Bus Interface with RS-485 Interface .....................................................................17
Figure 5.2 - Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface ...............................................................18
Figure 5.3 - High Speed CPU Bus Timing – Intel CPU Mode ......................................................................................20
Figure 5.4 - COM20022I 3V Network Using RS-485 Differential Transceivers...............................................................22
Figure 5.5 - Dipluse Waveform for Data of 1-1-0 ...........................................................................................................22
Figure 5.6 - Internal Block Diagram...............................................................................................................................24
Figure 6.1 - Sequential Access Operation.....................................................................................................................39
Figure 6.2 - RAM Buffer Packet Configuration ..............................................................................................................42
Figure 6.3 - Command Chaining Status Register Queue...............................................................................................44
Figure 7.1 - AC Measurements ....................................................................................................................................52
Figure 8.1 - Multiplexed Bus, 68XX-Like Control Signals; Read Cycle ........................................................................53
Figure 8.2 - Multiplexed Bus, 80XX-Like Control Signals; Read Cycle ........................................................................54
Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals; Write Cycle.........................................................................55
Figure 8.4 - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.........................................................................56
Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................57
Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................58
Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................59
Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................60
Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.................................................................61
Figure 8.10 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle ...............................................................62
Figure 8.11 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle ...............................................................63
Figure 8.12 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle ...............................................................64
Figure 8.13 - Normal Mode Transmit or Receive Timing..............................................................................................65
Figure 8.14 - Backplane Mode Transmit or Receive Timing ........................................................................................66
Figure 8.15 - TTL Input Timing on XTAL1 Pin..............................................................................................................67
Figure 8.16 - Reset and Interrupt Timing .....................................................................................................................67
Figure 8.17 - 48 Pin TQFP Package Outline ................................................................................................................68
Figure 9.1 - Effect of the EF Bit on the TA/RI Bit..........................................................................................................71
Figure 10.1 - Example of Interface of Circuit Diagram to ISA Bus................................................................................72
LIST OF TABLES
Table 5.1 - Typical Media .............................................................................................................................................24
Table 6.1 - Read Register Summary............................................................................................................................25
Table 6.2 - Data Register at 16 Bit Access ..................................................................................................................26
Table 6.3 - Write Register Summary ............................................................................................................................26
Table 6.4 - Data Register at 16 Bit Address .................................................................................................................26
Table 6.5 - Status Register ...........................................................................................................................................30
Table 6.6 - Diagnostic Status Register..........................................................................................................................31
Table 6.7 - Command Register.....................................................................................................................................32
Table 6.8 - Address Pointer High Register ....................................................................................................................33
Table 6.9 - Address Pointer Low Register.....................................................................................................................33
Table 6.10 - Sub Address Register ...............................................................................................................................34
Table 6.11 - Configuration Register ..............................................................................................................................34
Table 6.12 - Setup 1 Register .......................................................................................................................................36
Table 6.13 - Setup 2 Register .......................................................................................................................................37
Table 6.14 - Bus Control Register.................................................................................................................................38
Table 8.1 - 48 Pin TQFP Package Parameters ............................................................................................................68
SMSC COM20022I 3.3V Rev.C
Page 5
DATASHEET
Revision 03-08-07