COM20022I-3.3V Datasheet, PDF (26/73 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
READ
REGISTER
MSB
BUS
W16
X
X
X
X
X
X
CONTROL
Note 6.1 These bits can be written and read. For more information see Appendix C
LSB
X
ADDR
07-5
Table 6.2 - Data Register at 16 Bit Access
REGISTER
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT ADDR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
04
ADDR
MSB
00
RI/TR1
0
01
C7
C6
02
RD-DATA
AUTO-
INC
03
A7
A6
04
D7
D6
05
(R/W)
(R/W)
(Note 6.2)
(Note 6.2)
06
RESET
CCHEN
07-0
07-1
07-2
07-3
07-4
07-5
TID7
NID7
P1-MODE
0
RBUS-
TMG
W16
TID6
NID6
FOUR
NAKS
0
0
0
Table 6.3 - Write Register Summary
WRITE
0
0
EXCNAK
RECON
C5
C4
C3
C2
0
0
0
A10
A5
A4
A3
A2
D5
D4
D3
D2
0
0
0
SUB-AD2
TXEN
TID5
NID5
0
0
CKUP1
0
ET1
TID4
NID4
RCV-
ALL
0
CKUP0
0
ET2
TID3
NID3
CKP3
0
EF
0
BACK-
PLANE
TID2
NID2
CKP2
0
NO-
SYNC
0
NEW
NEXTID
C1
A9
A1
D1
SUB- AD1
SUB-
AD1
TID1
NID1
CKP1
0
RCN-
TM1
0
LSB
TA/
TTA
C0
A8
A0/ SWAP
D0
SUB-
AD0
SUB-
AD0
TID0
NID0
SLOW-ARB
REGISTER
INTERRUPT
MASK
COMMAND
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA
*See Table 6.4
SUBADR
CONFIG-
URATION
TENTID
NODEID
SETUP1
0
RCN-
TM0
0
TEST
SETUP2
BUS
CONTROL
Note 6.2 These bits can be written and read. For more information see Appendix C
REGISTER
DATA
Table 6.4 - Data Register at 16 Bit Address
BIT
BIT
BIT
BIT
BIT
BIT BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 ADDR
15
14
13
12
11
10
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
04
Revision 03-08-07
Page 26
DATASHEET
SMSC COM20022I 3.3V Rev.C