COM20022I-3.3V Datasheet, PDF (3/73 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
TABLE OF CONTENTS
Chapter 1 General Description ............................................................................................................. 6
Chapter 2 Pin Configuration................................................................................................................. 7
Chapter 3 Description of Pin Functions ............................................................................................... 8
Chapter 4 Protocol Description........................................................................................................... 11
4.1 Network Protocol ............................................................................................................................... 11
4.2 Data Rates......................................................................................................................................... 11
4.2.1 Selecting Clock Frequencies Above 2.5 Mbps .......................................................................................11
4.3 Network Reconfiguration ................................................................................................................... 12
4.4 Broadcast Messages......................................................................................................................... 13
4.5 Extended Timeout Function .............................................................................................................. 13
4.5.1 Response Time.......................................................................................................................................13
4.5.2 Idle Time.................................................................................................................................................13
4.5.3 Reconfiguration Time..............................................................................................................................13
4.6 Line Protocol ..................................................................................................................................... 13
4.6.1 Invitations To Transmit ...........................................................................................................................14
4.6.2 Free Buffer Enquiries..............................................................................................................................14
4.6.3 Data Packets ..........................................................................................................................................14
4.6.4 Acknowledgements.................................................................................................................................15
4.6.5 Negative Acknowledgements .................................................................................................................15
Chapter 5 System Description............................................................................................................. 16
5.1 Microcontroller Interface.................................................................................................................... 16
5.1.1 Selection of 8/16-Bit Access ...................................................................................................................19
5.1.2 High Speed CPU Bus Timing Support ....................................................................................................19
5.2 Transmission Media Interface ........................................................................................................... 21
5.2.1 Traditional Hybrid Interface.....................................................................................................................21
5.2.2 Backplane Configuration.........................................................................................................................21
5.2.3 Differential Driver Configuration..............................................................................................................23
5.2.4 Programmable TXEN Polarity.................................................................................................................23
Chapter 6 Functional Description....................................................................................................... 25
6.1 Microsequencer................................................................................................................................. 25
6.2 Internal Registers .............................................................................................................................. 27
6.2.1 Interrupt Mask Register (IMR) ................................................................................................................27
6.2.2 Data Register..........................................................................................................................................27
6.2.3 Tentative ID Register ..............................................................................................................................27
6.2.4 Node ID Register ....................................................................................................................................28
6.2.5 Next ID Register .....................................................................................................................................28
6.2.6 Status Register .......................................................................................................................................28
6.2.7 Diagnostic Status Register .....................................................................................................................28
6.2.8 Command Register.................................................................................................................................28
6.2.9 Address Pointer Registers ......................................................................................................................29
6.2.10 Configuration Register ........................................................................................................................29
6.2.11 Sub-Address Register .........................................................................................................................29
6.2.12 Setup 1 Register .................................................................................................................................29
6.2.13 Setup 2 Register .................................................................................................................................29
6.2.14 Bus Control Register ...........................................................................................................................30
6.3 Internal RAM...................................................................................................................................... 39
6.3.1 Sequential Access Memory ....................................................................................................................39
6.3.2 Access Speed.........................................................................................................................................40
6.3.3 Software Interface...................................................................................................................................40
6.3.4 Selecting RAM Page Size.......................................................................................................................40
6.3.5 Transmit Sequence.................................................................................................................................42
6.3.6 Receive Sequence..................................................................................................................................43
6.4 Command Chaining........................................................................................................................... 44
SMSC COM20022I 3.3V Rev.C
Page 3
DATASHEET
Revision 03-08-07