COM20022I-3.3V Datasheet, PDF (19/73 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
5.1.1 Selection of 8/16-Bit Access
The interface to the internal RAM is software selectable as either 8 or 16-bit. This feature is new to the
COM20022I 3V. The D15-D8 pins are the upper-byte data bus pins. The nIOCS16 pin is the 16-bit I/O
access enable output pin. This pin is active low for a 16-bit RAM access by the CPU.
The 16-bit access mode is enabled and disabled through the W16 bit located in the Bus Control Register
at bit 7. The SWAP bit is used to swap the upper and lower data bytes in 16-bit mode, as shown in the
table below. The SWAP bit is located at bit 0 of Address Low Pointer. This location is same as the A0 bit;
when 16 bit access is enabled (W16 =1), the A0 bit becomes the SWAP bit.
DETECTED HOST I/F MODE
Intel 80xx Mode
(RD,WR Mode)
Motorola 68xx Mode
(DIR, DS Mode)
SWAP BIT (NOTE)
0
1
0
1
Note: The SWAP bit is undefined after a hardware reset
D15-D8 PINS
Odd
Even
Even
Odd
D7-D0 PINS
Even
Odd
Odd
Even
As shown on the table above, even address data is to/from D7-D0 pins and odd address data is to/from
D15-D8 pins when detected host interface mode is Intel 80xx mode and the SWAP bit is not set. The odd
address data is to/from the D7-D0 pins and the even address data is to/from D15-D8 pins when detected
host interface mode is Motorola 68xx mode and the SWAP bit is not set.
When disabling 16-bit access, the D15-D8 pins are always Hi-Z. The D15-D8 pins are Hi-Z when enabling
16-bit access except for internal RAM access.
W16 bit and SWAP bit influence DATA register access only.
5.1.2 High Speed CPU Bus Timing Support
High speed CPU bus support was added to the COM20022I 3V. The reasoning behind this is as follows:
With the Host interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable
before the read signal is active and remain after the read signal is inactive. But the High Speed CPU bus
timing doesn't adhere to these timings. For example, a RISC type single chip microcontroller (like the
HITACHI SH-1 series) changes I/O address at the same time as the read signal. Therefore, several
external logic ICs would be required to connect to this microcontroller.
In addition, the Diagnostic Status (DIAG) register is cleared automatically by reading itself. The internal
DIAG register read signal is generated by decoding the Address (A2-A0), Chip Select (nCS) and Read
(nRD) signals. The decoder will generate a noise spike at the above tight timing. The DIAG register is
cleared by the spike signal without reading itself. This is unexpected operation. Reading the internal RAM
and Next Id Register have the same mechanism as reading the DIAG register.
Therefore, the address decode and host interface mode blocks were modified to fit the above CPU
interface to support high speed CPU bus timing. In Intel CPU mode (nRD, nWR mode), 3 bit I/O address
(A2-A0) and Chip Select (nCS) are sampled internally by Flip-Flops on the falling edge of the internal
delayed nRD signal. The internal real read signal is the more delayed nRD signal. But the rising edge of
nRD doesn't delay. By this modification, the internal real address and Chip Select are stable while the
internal real read signal is active. Refer to Figure 5.3.
SMSC COM20022I 3.3V Rev.C
Page 19
DATASHEET
Revision 03-08-07