COM20022I-3.3V Datasheet, PDF (29/73 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
6.2.9 Address Pointer Registers
These read/write registers are each 8-bits wide and are used for addressing the internal RAM. New pointer
addresses should be written by first writing to the High Register and then writing to the Low Register
because writing to the Low Register loads the address. The contents of the Address Pointer High and Low
Registers are undefined upon hardware reset. Writing to Address Pointer low loads the address.
The SWAP bit (new to the COM20022I 3V) is located at bit 0 of Address Pointer Low register. The SWAP bit
is used to swap the upper and lower data byte. When 16 bit access is enabled, (W16=1), A0 becomes the
SWAP bit.
6.2.10 Configuration Register
The Configuration Register is a read/write register which is used to configure the different modes of the
COM20022I 3V. The Configuration Register defaults to the value 0001 1000 upon hardware reset only.
SUBAD0 and SUBAD1 point to the selection in Register 7.
6.2.11 Sub-Address Register
The sub-address register is new to the COM20022I 3V, previously a reserved register. Bits 2, 1 and 0 are
used to select one of the registers assigned to address 7h. SUBAD1 and SUBAD0 already exist in the
Configuration register on the COM20020B. They are exactly same as those in the Configuration register.
If the SUBAD1 and SUBAD0 bits in the Configuration register are changed, the SUBAD1and SUBAD0 in
the Sub-Address register are also changed. SUBAD2 is a new sub-address bit. It Is used to access the 2
new Set Up registers, SETUP2 and BUS CONTROL. These registers are selected by setting SUBAD2=1.
The SUBAD2 bit is cleared automatically by writing the Configuration register.
Write Bits[7:3] to ‘0’ for proper operation.
6.2.12 Setup 1 Register
The Setup 1 Register is a read/write 8-bit register accessed when the Sub Address Bits are set up
accordingly (see the bit definitions of the Configuration Register). The Setup 1 Register allows the user to
change the network speed (data rate) or the arbitration speed independently, invoke the Receive All
feature and change the nPULSE1 driver type. The data rate may be slowed to 156.25Kbps and/or the
arbitration speed may be slowed by a factor of two. The Setup 1 Register defaults to the value 0000 0000
upon hardware reset only.
6.2.13 Setup 2 Register
The Setup 2 Register is new to the COM20022I 3V. It is an 8-bit read/write register accessed when the
Sub Address Bits SUBAD[2:0] are set up accordingly (see the bit definitions of the Sub Address Register).
This register contains bits for various functions. The CKUP1,0 bits select the clock to be generated from
the 20 MHz crystal. The RBUSTMG bit is used to Disable/Enable Fast Read function for High Speed CPU
bus support. The EF bit is used to enable the new timing for certain functions in the COM20022I 3V (if EF
= 0, the timing is the same as in the COM20020 Rev. B). See Appendix “A”. The NOSYNC bit is used to
enable the NOSYNC function during initialization. If this bit is reset, the line has to be idle for the RAM
initialization sequence to be written. If set, the line does not have to be idle for the initialization sequence
to be written. See Appendix “A”.
The RCNTM[1,0] bits are used to set the time-out period of the recon timer. Programming this timer for
shorter time periods has the benefit of shortened network reconfiguration periods. The time periods shown
SMSC COM20022I 3.3V Rev.C
Page 29
DATASHEET
Revision 03-08-07