91C100FDREVB Datasheet, PDF (68/68 Pages) SMSC Corporation – FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

LAN91C100FD REV. B REVISIONS
PAGE(S)
5
20
64
SECTION/FIGURE/ENTRY
Description of Pin Functions
Table under Bank 0
DC Electrical and Timing
Section
CORRECTION
Pin 175 – Changed to active high signal.
Changed RX_OVRN to 0 on High Byte row.
Removed references to RX_OVRN under table.
Updated SRAM Interface Timing information. Added
additional timing parameters. Please refer to the
application note titled “LAN91C100FD Minimum
SRAM Access Time Requirement and a List of
Recommended SRAMS” for additional details.
DATE
REVISED
05/31/00
05/31/00
12/17/99
SMSC DS – LAN91C100FD REV. B
Page 68
Rev. 05/31/2000