91C100FDREVB Datasheet, PDF (47/68 Pages) SMSC Corporation – FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

readback as both bits high. No other bits of the LAN91C100FD can be read or written until the EEPROM operation
completes and both bits are clear. This mechanism is also valid for reset initiated reloads.
Note: If no EEPROM is connected to the LAN91C100FD, for example for some embedded applications, the ENEEP pin
should be grounded and no accesses to the EEPROM will be attempted. Configuration, Base, and Individual Address
assume their default values upon hardware reset and the CPU is responsible for programming them for their final value.
IOS2-0
000
001
010
011
100
101
110
WORD ADDRESS
0h
1h
4h
5h
8h
9h
Ch
Dh
10h
11h
14h
15h
18h
19h
16 BITS
CONFIGURATION REG.
BASE REG.
CONFIGURATION REG.
BASE REG.
CONFIGURATION REG.
BASE REG.
CONFIGURATION REG.
BASE REG.
CONFIGURATION REG.
BASE REG.
CONFIGURATION REG.
BASE REG.
CONFIGURATION REG.
BASE REG.
XXX
20h
21h
22h
IA0-1
IA2-3
IA4-5
FIGURE 12 - 64 X 16 SERIAL EEPROM MAP
SMSC DS – LAN91C100FD REV. B
Page 47
Rev. 05/31/2000