91C100FDREVB Datasheet, PDF (51/68 Pages) SMSC Corporation – FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

HIGH-END ISA OR NON-BURST EISA MACHINES
On ISA machines, the LAN91C100FD is accessed as a 16 bit peripheral. No support for XT (8 bit peripheral) is provided.
The signal connections are listed in the following table:
ISA BUS
SIGNAL
Table 4 - High-End ISA or Non-Burst EISA Machines Signal Connectors
LAN91C100FD
SIGNAL
NOTES
A1-A15
A1-A15
Address bus used for I/O space and register decoding.
AEN
AEN
Qualifies valid I/O decoding - enabled access when low.
nIORD
nRD
I/O Read strobe - asynchronous read accesses. Address is valid
before leading edge.
nIOWR
IOCHRDY
nWR
ARDY
I/O Write strobe - asynchronous write access. Address is valid
before leading edge. Data is latched on trailing edge.
This signal is negated on leading nRD, nWR if necessary. It is then
asserted on CLK rising edge after the access condition is satisfied.
RESET
RESET
A0
nBE0
nSBHE
nBE1
IRQn
INTR0-INTR3
D0-D15
D0-D15
16 bit data bus. The bus byte(s) used to access the device are a
function of nBE0 and nBE1:
nBE0 nBE1 D0-D7
D8-D15
0 0 Lower
Upper
0 1 Lower
Not used
1 0 Not used Upper
nIOCS16
GND
VCC
nLDEV buffered
LCLK nADS
nBE2 nBE3
nCYCLE W/nR
nRDYRTN
Not used = tri-state on reads, ignored on writes
nLDEV is a totem pole output. Must be buffered using an open
collector driver. nLDEV is active on valid decodes of A15-A4 and
AEN=0.
UNUSED PINS
No upper word access.
SMSC DS – LAN91C100FD REV. B
Page 51
Rev. 05/31/2000