91C100FDREVB Datasheet, PDF (62/68 Pages) SMSC Corporation – FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

nADS
ADDRESS
t8
t9
A1-A15, AEN, nBE0-nBE3
nLDEV
t25
FIGURE 21 - ADDRESS LATCHING FOR ALL MODES
PARAMETER
t8 A1-A15, AEN, nBE0-nBE3 Setup to nADS Rising
t9 A1-A15, AEN, nBE0-nBE3 Hold After nADS Rising
t25 A4-A15, AEN to nLDEV Delay
MIN TYP MAX
10
15
20
UNITS
ns
ns
ns
LCLK
W/nR
ADDRESS
nADS
nCYCLE
WRITE DATA
nSRDY
nDATACS
t18
t20
t17A
t9
A1-A15, AEN, nBE0-nBE3
t8
t11
t16
t10
D0-D31 valid
t21
t21
RE 22 - SYNCHRONOUS WRITE CYCLE - nVLBUS=0
FIGU
t8
t9
t10
t11
t16
t17A
t18
t20
t21
PARAMETER
A1-A15, AEN, nBE0-nBE3 Setup to nADS Rising
A1-A15, AEN, nBE0-nBE3 Hold After nADS Rising
nCYCLE Setup to LCLK Rising
nCYCLE Hold after LCLK Rising (Non-Burst Mode)
W/nR Setup to nCYCLE Active
W/nR Hold after LCLK Rising with nLRDY Active
Data Setup to LCLK Rising (Write)
Data Hold from LCLK Rising (Write)
nLRDY Delay from LCLK Rising
MIN TYP MAX UNITS
10
ns
15
ns
7
ns
3
ns
30
ns
5
ns
13
ns
5
ns
10
ns
SMSC DS – LAN91C100FD REV. B
Page 62
Rev. 05/31/2000