91C100FDREVB Datasheet, PDF (60/68 Pages) SMSC Corporation – FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

t2
nDATACS
nADS
READ DATA
t3
t4
nRD, nWR
t1
WRITE DATA
t5
t5A
D0-D31 valid
FIGURE 18 - ASYNCHRONOUS CYCLE - nADS=0
(nDATACS Used to Select Data Register; Must Be 32 Bit Access)
PARAMETER
t1 A1-A15, AEN, nBE0-nBE3 Valid and nADS Low Setup to
nRD, nWR Active
t2 A1-A15, AEN, nBE0-nBE3 Hold After nRD, nWR Inactive
(Assuming nADS Tied Low)
t3 nRD Low to Valid Data
t4 nRD High to Data Floating
t5 Data Setup to nWR Inactive
t5A Data Hold After nWR Inactive
MIN TYP MAX UNITS
25
ns
20
ns
40
ns
30
ns
30
ns
5
ns
SMSC DS – LAN91C100FD REV. B
Page 60
Rev. 05/31/2000