91C100FDREVB Datasheet, PDF (63/68 Pages) SMSC Corporation – FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

LCLK
W/nR
ADDRES
nADS
nCYCL
READ
nSRD
RDYRT
nDATAC
t23
t24
t9
A1-A15, AEN, nBE0-nBE3
t8
t10
t16
t11
D0-D31
t21
t21
FIGURE 23 - SYNCHRONOUS READ CYCLE - nVLBUS=0
PARAMETER
t8 A1-A15, AEN, nBE0-nBE3 Setup to nADS Rising
t9 A1-A15, AEN, nBE0-nBE3 Hold After nADS Rising
t10 nCYCLE Setup to LCLK Rising
t11 nCYCLE Hold after LCLK Rising (Non-Burst Mode)
t16 W/nR Setup to nCYCLE Active
t20 Data Hold from LCLK Rising (Read)
t21 nLRDY Delay from LCLK Rising
t23 nRDYRTN Setup to LCLK Rising
t24 nRDYRTN Hold after LCLK Rising
MIN TYP MAX
10
15
7
3
30
5
10
7
3
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
SMSC DS – LAN91C100FD REV. B
Page 63
Rev. 05/31/2000