91C100FDREVB Datasheet, PDF (13/68 Pages) SMSC Corporation – FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

MMU BlockMMU
The Hardware Memory Management Unit allocates memory and transmit and receive packet queues. It also determines
the value of the transmit and receive interrupts as a function of the queues. The page size is 2k, with a maximum memory
size of 128k. MIR and MCR values are interpreted in 512 byte units.
BIU BlockBIU
The Bus Interface Unit can handle synchronous as well as asynchronous buses; different signals are used for each one.
Transparent latches are added on the address path using rising nADS for latching.
When working with an asynchronous bus like ISA, the read and write operations are controlled by the edges of nRD and
nWR. ARDY is used for notifying the system that it should extend the access cycle. The leading edge of ARDY is
generated by the leading edge of nRD or nWR while the trailing edge of ARDY is controlled by the internal LAN91C100FD
clock and, therefore, asynchronous to the bus.
In the synchronous VL Bus type mode, nCYCLE and LCLK are used to for read and write operations. Completion of the
cycle may be determined by using nSRDY. nSRDY is controlled by LCLK and synchronous to the bus.
Direct 32 bit access to the Data Path is supported by using the nDATACS input. By asserting nDATACS, external DMA
type of devices will bypass the BIU address decoders and can sequentially access memory with no CPU intervention.
nDATACS accesses can be used in the EISA DMA burst mode (nVLBUS=1) or in asynchronous cycles. These cycles
MUST be 32 bit cycles. Please refer to the corresponding timing diagrams for details on these cycles.
The BIU is implemented using the following principles:
1) Address decoding is based on the values of A15-A4 and AEN.
2) Address latching is performed by using transparent latches that are transparent when nADS=0 and nRD=1, nWR=1
and latch on nADS rising edge.
3) Byte, word and doubleword accesses to all registers and Data Path are supported except a doubleword write to offset
Ch will only write the BANK SELECT REGISTER (offset Fh).
4) No bus byte swapping is implemented (no eight bit mode).
5) Word swapping as a function of A1 is implemented for 16 bit bus support.
6) The asynchronous interface uses nRD and nWR strobes. If necessary, ARDY is negated on the leading edge of the
strobe. The ARDY trailing edge is controlled by CLK.
7) The VLBUS synchronous interface uses LCLK, nADS, and W/nR as defined in the VESA specification as well as
nCYCLE to control read and write operations and generate nSRDY.
8) EISA burst DMA cycles to and from the DATA REGISTER are supported as defined in the EISA Slave Mode "C"
specification when nDATACS is driven by nDAK.
9) Synchronous and asynchronous cycles can be mixed as long as they are not active simultaneously.
10) Address and bank selection can be bypassed to generate 32 bit Data Path accesses by activating the nDATACS pin.
MAC-PHY Interface BlockMAC-PHY INTERFACE
Two separate interfaces are defined, one for the 10 Mbps bit rate interface and one for the MII 100 Mbps and 10 Mbps
nibble rate interface. The 10 Mbps ENDEC interface comprises the signals used for interfacing Ethernet ENDECs. The 100
Mbps interface follows the MII for 100 Mbps 802.3 networks proposal, and it is based on transferring nibbles between the
MAC and the PHY.
For the MII interface, transmit data is clocked out using the TX25 clock input, while receive data is clocked in using RX25.
In 100 Mbps mode, the LAN91C100FD provides the following interface signals to the PHY:
SMSC DS – LAN91C100FD REV. B
Page 13
Rev. 05/31/2000