91C100FDREVB Datasheet, PDF (65/68 Pages) SMSC Corporation – FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

TXC
TXEN
TXD
t30
t30
t30
RXD
RXC
CRS
FIGURE 25 - ENDEC INTERFACE - 10 MBPS
PARAMETER
t30 TXD, TXEN Delay from TXC Rising
t31 RXD Setup to RXC Rising
t32 RXD Hold After RXC Rising
MIN TYP
0
10
30
Notes:
1. CRS input might be asynchronous to RXC.
2. RXC starts after CRS goes active. RXC stops after CRS goes inactive.
3. COL is an asynchronous input.
MAX
40
t31
t32
UNITS
ns
ns
ns
t27
TXD0-TXD3
t27
TXEN100
RXD0-RXD3
RX25
RX_DV
RX_ER
t28
t28
t28
t29
t29
FIGURE 26 - MII INTERFACE
PARAMETER
t27 TXD0-TXD3, TXEN100 Delay from TX25 Rising
t28 RXD0-RXD3, RX_DV, RX_ER Setup to RX25 Rising
t29 RXD0-RXD3, RX_DV, RX_ER Hold After RX25 Rising
MIN TYP MAX
0
15
10
10
UNITS
ns
ns
ns
SMSC DS – LAN91C100FD REV. B
Page 65
Rev. 05/31/2000