91C100FDREVB Datasheet, PDF (14/68 Pages) SMSC Corporation – FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

For transmission: TXEN100 TXD0-3 TX25
For reception: RX_DV RX_ER RXD0-3 RX25
For CSMA/CD state machines: CRS100 COL100
A transmission begins by TXEN100 going active (high), and TXD0-TXD3 having the first valid preamble nibble. TXD0
carries the least significant bit of the nibble (that is the one that would go first out of the EPH at 100 Mbps), while TXD3
carries the most significant bit of the nibble. TXEN100 and TXD0-TXD3 are clocked by the LAN91C100FD using TX25
rising edges. TXEN100 goes inactive at the end of the packet on the last nibble of the CRC.
During a transmission, COL100 might become active to indicate a collision. COL100 is asynchronous to the
LAN91C100FD’s clocks and will be synchronized internally to TX25.
Reception begins when RX_DV (receive data valid) is asserted. A preamble pattern or flag octet will be present at RXD0-
RXD3 when RX_DV is activated. The LAN91C100FD requires no training sequence beyond a full flag octet for reception.
RX_DV as well as RXD0-RXD3 are sampled on RX25 rising edges. RXD0 carries the least significant bit and RXD3 the
most significant bit of the nibble. RX_DV goes inactive when the last valid nibble of the packet (CRC) is presented at
RXD0-RXD3.
RX_ER might be asserted during packet reception to signal the LAN91C100FD that the present receive packet is invalid.
The LAN91C100FD will discard the packet by treating it as a CRC error.
When MIISEL=1, RXD0-RXD3 should always be aligned to packet nibbles, therefore, opening flag detection does not
consider misaligned cases. Opening flag detection expects the 5Dh pattern and will not reject the packet on non-preamble
patterns. When MIISEL=0 the opening flag detection expects a "10101011" pattern and will use it for determining nibble
alignment.
CRS100 is used as a frame envelope signal for the CSMA/CD MAC state machines (deferal and backoff functions), but it is
not used for receive framing functions. CRS100 is an asynchronous signal and it will be active whenever there is activity on
the cable, including LAN91C100FD transmissions and collisions.
Switching between the ENDEC and MII interfaces is controlled by the MII SELECT bit in the CONFIG REGISTER. The
MIISEL pin reflects the value of this bit and may be used to control external multiplexing logic.
Note that given the modular nature of the MII, TX25 and RX25 cannot be assumed to be free running clocks. The
LAN91C100FD will not rely on the presence of TX25 and RX25 during reset and will use its own internal clock whenever a
timeout on TX25 is detected.
MII Management Interface Block
PHY management through the MII management interface is supported by the LAN91C100FD by providing the means to
drive a tri-statable data output, a clock, and reading an input. Timing and framing for each management command is to be
generated by the CPU.
Serial EEPROM Interface
This block is responsible for reading the serial EEPROM upon hardware reset (or equivalent command) and defining
defaults for some key registers. A write operation is also implemented by this block, that under CPU command will program
specific locations in the EEPROM. This block is an autonomous state machine and controls the internal Data Bus of the
LAN91C100FD during active operation.
SMSC DS – LAN91C100FD REV. B
Page 14
Rev. 05/31/2000