91C100FDREVB Datasheet, PDF (59/68 Pages) SMSC Corporation – FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

TIMING DIAGRAMS
ADDRESS
nADS
t2
A1-15, AEN, nBE0-nBE3 valid
READ DATA
t3
t4
nRD,nWR
t1
WRITE DATA
t5
t5A
D0-D31 valid
FIGURE 16 - ASYNCHRONOUS CYCLE - nADS=0
PARAMETER
t1 A1-A15, AEN, nBE0-nBE3 Valid and nADS Low Setup to
nRD, nWR Active
t2 A1-A15, AEN, nBE0-nBE3 Hold After nRD, nWR Inactive
(Assuming nADS Tied Low)
t3 nRD Low to Valid Data
t4 nRD High to Data Floating
t5 Data Setup to nWR Inactive
t5A Data Hold After nWR Inactive
MIN TYP MAX UNITS
25
ns
20
ns
40
ns
30
ns
30
ns
5
ns
ADDRESS
nADS
READ DATA
nRD, nWR
WRITE DATA
A1-A15, AEN, nBE0-nBE3
valid
t8
t9
t3
t4
t1
t5
t5A
D0-D31 ^valid
FIGURE 17 - ASYNCHRONOUS CYCLE - USING nADS
PARAMETER
MIN TYP MAX UNITS
t1 A1-A15, AEN, nBE0-nBE3 Valid and nADS Low Setup to nRD, 25
ns
nWR Active
t3 nRD Low to Valid Data
40
ns
t4 nRD High to Data Floating
30
ns
t5 Data Setup to nWR Inactive
30
ns
t5A Data Hold After nWR Inactive
5
ns
t8 A1-A15, AEN, nBE0-nBE3 Setup to nADS Rising
10
ns
t9 A1-A15, AEN, nBE0-nBE3 Hold after nADS Rising
15
ns
SMSC DS – LAN91C100FD REV. B
Page 59
Rev. 05/31/2000