91C100FDREVB Datasheet, PDF (5/68 Pages) SMSC Corporation – FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

PQFP/TQFP
PIN NO.
148-159
145-147
193
160-163
173-170,
168-166,
164, 144,
142-139,
137-135,
133,
131-129,
127, 126,
124, 123,
121, 118,
117,
115-112, 110
182
95
183
184
181
105
175
106
NAME
Address
Address
Address
Enable
nByte
Enable
Data Bus
Reset
nAddress
Strobe
nCycle
Write/
nRead
nVL Bus
Access
Local Bus
Clock
Asynchron-
ous Ready
nSynchron
-
ous Ready
DESCRIPTION OF PIN FUNCTIONS
BUFFER
SYMBOL TYPE
DESCRIPTION
A4-A15
I
Input. Decoded by LAN91C100FD to determine
access to its registers.
A1-A3
I
Input. Used by LAN91C100FD for internal register
selection.
AEN
I
Input. Used as an address qualifier. Address
decoding is only enabled when AEN is low.
nBE0-
I
Input. Used during LAN91C100FD register
nBE3
accesses to determine the width of the access and
the register(s) being accessed. nBE0-nBE3 are
ignored when nDATACS is low (burst accesses)
because 32 bit transfers are assumed.
D0-D31
I/O24 Bidirectional. 32 bit data bus used to access the
LAN91C100FD’s internal registers. Data bus has
weak internal pullups. Supports direct connection
to the system bus without external buffering. For
16 bit systems, only D0-D15 are used.
RESET
nADS
nCYCLE
W/nR
nVLBUS
LCLK
ARDY
nSRDY
IS
IS
I
IS
I with
pullup
I
OD16
O16
Input. This input is not considered active unless it
is active for at least 100ns to filter narrow glitches.
Input. For systems that require address latching,
the rising edge of nADS indicates the latching
moment for A1-A15 and AEN. All LAN91C100FD
internal functions of A1-A15, AEN are latched
except for nLDEV decoding.
Input. This active low signal is used to control
LAN91C100FD EISA burst mode synchronous bus
cycles.
Input. Defines the direction of synchronous cycles.
Write cycles when high, read cycles when low.
Input. When low, the LAN91C100FD synchronous
bus interface is configured for VL Bus accesses.
Otherwise, the LAN91C100FD is configured for
EISA DMA burst accesses. Does not affect the
asynchronous bus interface.
Input. Used to interface synchronous buses.
Maximum frequency is 50 MHz. Limited to 8.33
MHz for EISA DMA burst mode.
Open drain output. ARDY may be used when
interfacing asynchronous buses to extend
accesses. Its rising (access completion) edge is
controlled by the XTAL1 clock and, therefore,
asynchronous to the host CPU or bus clock.
Output. This output is used when interfacing
synchronous buses and nVLBUS=0 to extend
accesses. This signal remains normally inactive,
and its falling edge indicates completion. This
signal is synchronous to the bus clock LCLK.
SMSC DS – LAN91C100FD REV. B
Page 5
Rev. 05/31/2000