91C100FDREVB Datasheet, PDF (61/68 Pages) SMSC Corporation – FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

LCLK
t12
t13
nDATACS
t17
W/nR
t17
nCYCLE
WRITE DATA
t20
t18
a
b
c
nRDYRTN
t15
t14
FIGURE 19 - BURST WRITE CYCLES - nVLBUS=1
PARAMETER
t12 nDATACS Setup to Either nCYCLE or W/nR Falling
t13 nDATACS Hold after Either nCYCLE or W/nR Rising
t14 nRDYRTN Setup to LCLK Falling
t15 nRDYRTN Hold after LCLK Falling
t17 nCYCLE High and W/nR High Overlap
t18 Data Setup to LCLK Rising (Write)
t20 Data Hold from LCLK Rising (Write)
MIN TYP MAX UNITS
60
ns
30
ns
15
ns
2
ns
50
ns
13
ns
5
ns
LCLK
t12
t13
nDATACS
t17
W/nR
READ DATA
t19
a
b
c
nRDYRTN
t15
t14
t17
nCYCLE
FIGURE 20 - BURST READ CYCLES - nVLBUS=1
PARAMETER
t12 nDATACS Setup to Either nCYCLE or W/nR Falling
t13 nDATACS Hold after Either nCYCLE or W/nR Rising
t14 nRDYRTN Setup to LCLK Falling
t15 nRDYRTN Hold after LCLK Falling
t17 nCYCLE High and W/nR High Overlap
t19 Data Delay from LCLK Rising (Read)
Note *: (holdt.)
Note **: (Setupt.)
MIN TYP MAX
60
30
15
2
50
5*
38**
UNITS
ns
ns
ns
ns
ns
ns
SMSC DS – LAN91C100FD REV. B
Page 61
Rev. 05/31/2000