91C100FDREVB Datasheet, PDF (45/68 Pages) SMSC Corporation – FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

2) One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO RELEASE=1. TX EMPTY
INT is generated only after transmitting the last packet in the FIFO.
TX INT will be set on a fatal transmit error allowing the CPU to know that the transmit process has stopped and
therefore the FIFO will not be emptied.
This mode has the advantage of a smaller CPU overhead, and faster memory de-allocation. Note that when
AUTO RELEASE=1 the CPU is not provided with the packet numbers that completed successfully.
Note: The pointer register is shared by any process accessing the LAN91C100FD memory. In order to allow
processes to be interruptable, the interrupting process is responsible for reading the pointer value before modifying it,
saving it, and restoring it before returning from the interrupt.
Typically there would be three processes using the pointer:
1) Transmit loading (sometimes interrupt driven)
2) Receive unloading (interrupt driven)
3) Transmit Status reading (interrupt driven).
1) and 3) also share the usage of the Packet Number Register. Therefore saving and restoring the PNR is also
required from interrupt service routines.
INTERRUPT
STATUS REGISTER
RCV
INT
PACKET NUMBER
REGISTER
TWO
OPTIONS
TX EMPTY
INT
TX
INT
ALLOC
INT
TX
FIFO
'EMPTY'
TX COMPLETION
FIFO
'NOT EMPTY'
TX DONE
PACKET NUMBER
CPU ADDRESS
'NOT EMPTY'
RX FIFO
PACKET NUMBER
RX
FIFO
RX PACKET
NUMBER
CSMA ADDRESS
M.S. BIT ONLY
LOGICAL PACKET #
ADDRESS
PACK # OUT
MMU
PHYSICAL ADDRESS
CSMA/CD
RAM
FIGURE 11 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU
SMSC DS – LAN91C100FD REV. B
Page 45
Rev. 05/31/2000