91C100FDREVB Datasheet, PDF (20/68 Pages) SMSC Corporation – FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

STP_SQET - Stop transmission on SQET error. If set, stops and disables transmitter on SQE test error. Does not stop on
SQET error and transmits next frame if clear. Defaults low.
FDUPLX - When set it enables Full Duplex operation. This will cause frames to be received if they pass the address filter
regardless of the source for the frame. When clear the node will not receive a frame sourced by itself.
MON_CSN - When set the LAN91C100FD monitors carrier while transmitting. It must see its own carrier by the end of the
preamble. If it is not seen, or if carrier is lost during transmission, the transmitter aborts the frame without CRC and turns
itself off and sets the LOST CARR bit in the EPHSR. When this bit is clear the transmitter ignores its own carrier. Defaults
low. Should be 0 for MII operation.
NOCRC - Does not append CRC to transmitted frames when set. Allows software to insert the desired CRC. Defaults to
zero, namely CRC inserted.
PAD_EN - When set, the LAN91C100FD will pad transmit frames shorter than 64 bytes with 00. Does not pad frames
when reset
FORCOL - When set, the FORCOL bit will force a collision by not deferring deliberately. This bit is set and cleared only by
the CPU. When TXENA is enabled with no packets in the queue and while the FORCOL bit is set, the LAN91C100FD will
transmit a preamble pattern the next time a carrier is seen on the line. If a packet is queued, a preamble and SFD will be
transmitted. This bit defaults low to normal operation. NOTE: The LATCOL bit in the EPHSR, setting up as a result of
FORCOL, will reset TXENA to 0. In order to force another collision, TXENA must be set to 1 again.
LOOP - Loopback. General purpose output port used to control the LBK pin. Typically used to put the PHY chip in
loopback mode.
TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the LAN91C100FD will
complete the current transmission before stopping. When stopping due to an error, this bit is automatically cleared.
BANK 0
OFFSET
2
NAME
EPH STATUS REGISTER
TYPE
READ ONLY
SYMBOL
EPHSR
This register stores the status of the last transmitted frame. This register value, upon individual transmit packet completion,
is stored as the first word in the memory area allocated to the packet. Packet interrupt processing should use the copy in
memory as the register itself will be updated by subsequent packet transmissions. The register can be used for real time
values (like TXENA and LINK OK). If TXENA is cleared the register holds the last packet completion status.
HIGH
BYTE
LOW
BYTE
TX UNRN
LINK_
OK
0
-nLNK pin
TX
DEFR
LTX
BRD
0
0
0
0
SQET
0
CTR
_ROL
0
16COL
0
EXC
_DEF
0
LTX
MULT
0
LOST
CARR
0
MUL
COL
0
LATCOL
0
0
SNGL
COL
0
0
TX_SUC
0
TXUNRN - Transmit Under Run. Set if under run occurs, it also clears TXENA bit in TCR. Cleared by setting TXENA high.
This bit may only be set if early TX is being used.
LINK_OK - General purpose input port driven by nLNK pin inverted. Typically used for Link Test. A transition on the value
of this bit generates an interrupt.
CTR_ROL - Counter Roll Over. When set one or more 4 bit counters have reached maximum count (15). Cleared by
reading the ECR register.
SMSC DS – LAN91C100FD REV. B
Page 20
Rev. 05/31/2000