LAN9312 Datasheet, PDF (452/458 Pages) SMSC Corporation – High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

15.5.9
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
TX Data FIFO Direct PIO Write Cycle Timing
Please refer to Section 8.4.9, "TX Data FIFO Direct PIO Writes," on page 111 for a functional
description of this mode.
FIFO_SEL
A[2], END_SEL
t_asu
nCS, nWR
D[31:0]
t_cycle
t_ah
t_csl
t_csh
t_dsu
t_dh
Figure 15.9 TX Data FIFO Direct PIO Write Cycle Timing
Table 15.13 TX Data FIFO Direct PIO Write Cycle Timing Values
SYMBOL
t_cycle
t_csl
t_csh
t_asu
t_ah
t_dsu
t_dh
DESCRIPTION
Write Cycle Time
nCS, nWER Assertion Time
nCS, nWR De-assertion Time
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR De-assertion
Data Hold Time
MIN
TYP
45
32
13
0
0
7
0
MAX
UNITS
nS
nS
nS
nS
nS
nS
nS
Note: A TX Data FIFO direct PIO write cycle begins when both nCS and nWR are asserted. The
cycle ends when either or both nCS and nWR are de-asserted. They may be asserted and de-
asserted in any order.
Revision 1.2 (04-08-08)
452
DATASHEET
SMSC LAN9312