LAN9312 Datasheet, PDF (449/458 Pages) SMSC Corporation – High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
15.5.6 RX Data FIFO Direct PIO Read Cycle Timing
Please refer to Section 8.4.6, "RX Data FIFO Direct PIO Reads," on page 108 for a functional
description of this mode.
FIFO_SEL
A[x:2], END_SEL
nCS, nRD
D[31:0]
t_asu
t_csl
t_csdv
t_don
t_cycle
t_ah
t_csh
t_doff
t_doh
Figure 15.6 RX Data FIFO Direct PIO Read Cycle Timing
SYMBOL
t_cycle
t_csl
t_csh
t_csdv
t_asu
t_ah
t_don
t_doff
t_doh
Table 15.10 RX Data FIFO Direct PIO Read Cycle Timing Values
DESCRIPTION
Read Cycle Time
CS, nRD Assertion Time
nCS, nRD De-assertion Time
nCS, nRD Valid to Data Valid
Address, FIFO_SEL Setup to nCS, nRD Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
MIN
TYP
45
32
13
0
0
0
0
MAX
30
9
UNITS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Note: A RX Data FIFO direct PIO read cycle begins when both nCS and nRD are asserted. The cycle
ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order.
SMSC LAN9312
449
DATASHEET
Revision 1.2 (04-08-08)