LAN9312 Datasheet, PDF (259/458 Pages) SMSC Corporation – High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.2.9 Miscellaneous
This section details the remainder of the System CSR’s. These registers allow for monitoring and
configuration of various LAN9312 functions such as the Chip ID/revision, byte order testing, power
management, hardware configuration, general purpose timer, and free running counter.
14.2.9.1 Chip ID and Revision (ID_REV)
Offset:
050h
Size:
32 bits
This read-only register contains the ID and Revision fields for the LAN9312.
BITS
DESCRIPTION
31:16
15:0
Chip ID
This field indicates the chip ID.
Chip Revision
This field indicates the design revision.
Note 14.46 Default value is dependent on device revision.
TYPE
RO
DEFAULT
9312h
RO
Note 14.46
SMSC LAN9312
259
DATASHEET
Revision 1.2 (04-08-08)