LAN9312 Datasheet, PDF (381/458 Pages) SMSC Corporation – High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.5.3.13 Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA)
Register #:
1812h
Size:
32 bits
This register is used to write the DIFFSERV table. The DIFFSERV table is not initialized upon reset
on power-up. If DIFFSERV is enabled, the full table should be initialized by the host.
BITS
DESCRIPTION
31:3 RESERVED
2:0 DIFFSERV Priority
These bits specify the assigned receive priority for IP packets with a ToS/CS
field that matches this index.
TYPE
RO
R/W
DEFAULT
-
000b
SMSC LAN9312
381
DATASHEET
Revision 1.2 (04-08-08)