LAN9312 Datasheet, PDF (306/458 Pages) SMSC Corporation – High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.4.2.12 Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x)
Index (decimal): 30
Size:
16 bits
This read/write register is used to enable or mask the various Port x PHY interrupts and is used in
conjunction with the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).
BITS
DESCRIPTION
15:8 RESERVED
7 INT7_MASK
This interrupt mask bit enables/masks the ENERGYON interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
6 INT6_MASK
This interrupt mask bit enables/masks the Auto-Negotiation interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
5 INT5_MASK
This interrupt mask bit enables/masks the remote fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
4 INT4_MASK
This interrupt mask bit enables/masks the Link Down (link status negated)
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
3 INT3_MASK
This interrupt mask bit enables/masks the Auto-Negotiation LP acknowledge
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
2 INT2_MASK
This interrupt mask bit enables/masks the Parallel Detection fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
1 INT1_MASK
This interrupt mask bit enables/masks the Auto-Negotiation page received
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
0 RESERVED
TYPE
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
DEFAULT
-
0b
0b
0b
0b
0b
0b
0b
-
Revision 1.2 (04-08-08)
306
DATASHEET
SMSC LAN9312