LAN9312 Datasheet, PDF (414/458 Pages) SMSC Corporation – High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

14.5.4.3
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL)
Register #:
1C02h
Size:
32 bits
This register configures the buffer usage level when a Pause frame or backpressure is sent.
BITS
DESCRIPTION
31:16 RESERVED
15:8 Pause Level Low
These bits specify the buffer usage level during times when 2 or 3 ports are
active.
Each buffer is 128 bytes.
Note: A port is “active” when 36 buffers are in use for that port.
7:0 Pause Level High
These bits specify the buffer usage level during times when 1 port is active.
Each buffer is 128 bytes.
Note: A port is “active” when 36 buffers are in use for that port.
TYPE
RO
R/W
R/W
DEFAULT
-
21h
3Ch
Revision 1.2 (04-08-08)
414
DATASHEET
SMSC LAN9312