LAN9312 Datasheet, PDF (176/458 Pages) SMSC Corporation – High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
BITS
5
4
3
2:0
DESCRIPTION
RX Data FIFO Level Interrupt (RDFL)
This interrupt is generated when the RX Data FIFO reaches the
programmed level in the RX Space Available Level field of the FIFO Level
Interrupt Register (FIFO_INT).
RX Status FIFO Full Interrupt (RSFF)
This interrupt is generated when the RX Status FIFO is full.
RX Status FIFO Level Interrupt (RSFL)
This interrupt is generated when the RX Status FIFO reaches the
programmed level in the RX Status Level field of the FIFO Level Interrupt
Register (FIFO_INT).
RESERVED
TYPE
R/WC
R/WC
R/WC
RO
DEFAULT
0b
0b
0b
-
Revision 1.2 (04-08-08)
176
DATASHEET
SMSC LAN9312