LAN9312 Datasheet, PDF (17/458 Pages) SMSC Corporation – High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
MII
MIIM
MIL
MLD
MLT-3
msb
MSB
NRZI
N/A
NC
OUI
Outbound
PIO cycle
PISO
PLL
PTP
RESERVED
RTC
SA
SFD
SIPO
SMI
SQE
SSD
UDP
UUID
WORD
Media Independent Interface
Media Independent Interface Management
MAC Interface Layer
Multicast Listening Discovery
Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method
where a change in the logic level represents a code bit “1” and the logic
output remaining at the same level represents a code bit “0”.
Most Significant Bit
Most Significant Byte
Non Return to Zero Inverted. This encoding method inverts the signal for a
“1” and leaves the signal unchanged for a “0”
Not Applicable
No Connect
Organizationally Unique Identifier
Refers to data output from the LAN9312 to the host
Program I/O cycle. An SRAM-like read or write cycle on the HBI.
Parallel In Serial Out
Phase Locked Loop
Precision Time Protocol
Refers to a reserved bit field or address. Unless otherwise noted, reserved
bits must always be zero for write operations. Unless otherwise noted, values
are not guaranteed when reading reserved bits. Unless otherwise noted, do
not read or write to reserved addresses.
Real-Time Clock
Source Address
Start of Frame Delimiter - The 8-bit value indicating the end of the preamble
of an Ethernet frame.
Serial In Parallel Out
Serial Management Interface
Signal Quality Error (also known as “heartbeat”)
Start of Stream Delimiter
User Datagram Protocol - A connectionless protocol run on top of IP
networks
Universally Unique IDentifier
16-bits
SMSC LAN9312
17
DATASHEET
Revision 1.2 (04-08-08)