LAN9312 Datasheet, PDF (383/458 Pages) SMSC Corporation – High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.5.3.15 Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS)
Register #:
1814h
Size:
32 bits
This register indicates the current DIFFSERV command status.
BITS
DESCRIPTION
31:1 RESERVED
0 Operation Pending
When set, this bit indicates that the read or write command is taking place.
This bit is cleared once the command has finished.
TYPE
RO
RO
SC
DEFAULT
-
0b
SMSC LAN9312
383
DATASHEET
Revision 1.2 (04-08-08)