LAN9312 Datasheet, PDF (154/458 Pages) SMSC Corporation – High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Chapter 11 IEEE 1588 Hardware Time Stamp Unit
11.1
11.1.1
Functional Overview
The LAN9312 provides hardware support for the IEEE 1588 Precision Time Protocol (PTP), allowing
clock synchronization with remote Ethernet devices, packet time stamping, and time driven event
generation. Time stamping is supported on all ports, with an individual IEEE 1588 Time Stamp module
connected to each port via the MII bus. Any port may function as a master or a slave clock per the
IEEE 1588 specification, and the LAN9312 as a whole may function as a boundary clock.
A 64-bit tunable clock is provided that is used as the time source for all IEEE 1588 time stamp related
functions. An IEEE 1588 Clock/Events block provides IEEE 1588 clock comparison based interrupt
generation and time stamp related GPIO event generation. Two LAN9312 GPIO pins (GPIO[8:9]) can
be used to trigger a time stamp capture when configured as an input, or output a signal from the GPIO
based on an IEEE 1588 clock target compare event when configured as an output. Section 11.1.2,
"Block Diagram" describes the various IEEE 1588 related blocks and how they interface to other
LAN9312 functions.
All features of the IEEE 1588 hardware time stamp unit can be monitored and configured via their
respective configuration and status registers. A detailed description of all IEEE 1588 CSRs is included
in Section 14.2.5, "IEEE 1588," on page 201.
IEEE 1588
IEEE 1588 specifies a Precision Time Protocol (PTP) used by master and slave clock devices to pass
time information in order to achieve clock synchronization. Five network message types are defined:
„ Sync
„ Delay_Req
„ Follow_Up
„ Delay_Resp
„ Management
Only the first four message types (Sync, Delay_Req, Follow_Up, Delay_Resp) are used for clock
synchronization. Using these messages, the protocol software may calculate the offset and network
delay between time stamps, adjusting the slave clock frequency as needed. Refer to the IEEE 1588
protocol for message definitions and proper usage.
A PTP domain is segmented into PTP sub-domains, which are then segmented into PTP
communication paths. Within each PTP communication path there is a maximum of one master clock,
which is the source of time for each slave clock. The determination of which clock is the master and
which clock(s) is(are) the slave(s) is not fixed, but determined by the IEEE 1588 protocol. Similarly,
each PTP sub-domain may have only one master clock, referred to as the Grand Master Clock.
PTP communication paths are conceptually equivalent to Ethernet collision domains and may contain
devices which extend the network. However, unlike Ethernet collision domains, the PTP
communication path does not stop at a network switch, bridge, or router. This leads to a loss of
precision when the network switch/bridge/router introduces a variable delay. Boundary clocks are
defined which conceptually bypass the switch/bridge/router (either physically or via device integration).
Essentially, a boundary clock acts as a slave to an upstream master, and as a master to a down stream
slave. A boundary clock may contain multiple ports, but a maximum of one slave port is permitted.
For more information on the IEEE 1588 protocol, refer to the National Institute of Standards and
Technology IEEE 1588 website:
http://ieee1588.nist.gov/
Revision 1.2 (04-08-08)
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