SI5364 Datasheet, PDF (9/40 Pages) Silicon Laboratories – SONET/SDH PRECISION PORT CARD CLOCK IC

Si5364
Table 3. AC Characteristics (Continued)
(V_DD33 = 3.3 V ±5%, T_A = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Output Clock Duty Cycle
C_{DUTY_OU}
Differential:
48
—
52
%
T
(CLKOUT+) – (CLKOUT–
)
SYNCIN Pulse Width
FSYNC Frequency
t_SYNCIN
f_FSYNC
Figure 3
Figure 3
20
—
—
ns
—
f_{O_19}/
—
kHz
2430
FSYNC Pulse Width
SYNCIN to FSYNC
Phase Skew Between Outputs
RSTN/CAL Pulse Width
INCDELAY, DECDELAY Pulse
Width
t_{FSYNC_PW}
t_{SYNCIN_DL}
Y
t_skew
t_RSTN
t_INCDEC
Figure 3
Figure 3
Figure 5
— 16/f_{O_19} —
s
38
45
52
ns
—
—
400 ps
20
—
—
ns
1
—
—
µs
INCDELAY, DECDELAY Setup Time
INCDELAY, DECDELAY Hold Time
Transitionless Period Required on
CLKIN for Detecting an LOS Condi-
tion
t_SETUP
t_HOLD
t_LOS
Figure 5
Figure 5
Figure 4
1
—
—
µs
1
—
—
µs
24/
—
32/
s
f_{O_622}
f_{O_622}
Recovery Time for Clearing an LOS
t_VAL
or FOS Condition
Measured from when a
valid reference clock is
VALTIME = 0
VALTIME = 1
applied until the applica- _0.09
—
0.22
s
ble LOS or FOS flag
12.0
—
14.1
clears
*Note: The Si5364 provides a 1, 8, or 32x clock frequency multiplication function with an option for additional frequency
scaling by a factor of 255/238 or 238/255 for FEC rate compatibility.
Rev. 2.2
9