SI5364 Datasheet, PDF (7/40 Pages) Silicon Laboratories – SONET/SDH PRECISION PORT CARD CLOCK IC

Si5364
Table 2. DC Characteristics
(V_DD33 = 3.3 V ±5%, T_A = –20 to 85 °C)
Parameter
Symbol Test Condition Min Typ Max _Unit
Supply Current
Single Clock Output
Four Clock Outputs
I_DD
f_out = 19.44 MHz — 120 140
mA
— 212 240
Power Dissipation Using 3.3 V Supply
Single Clock Output
Four Clock Outputs
Common Mode Input Voltage^1,2,3
(CLKIN_A, CLKIN_B, REF/CLKIN_F)
Single-Ended Input Voltage^2,3,4
(CLKIN_A, CLKIN_B, REF/CLKIN_F)
Differential Input Voltage Swing^2,3,4
(CLKIN_A, CLKIN_B, REF/CLKIN_F)
P_D
V_ICM
V_IS
V_ID
f_out = 19.44 MHz
— 396 462 _mW
700 792
1.0 1.5 2.0
V
See Figure 1A 200
See Figure 1B 200
—
500⁴ _mVPP
—
500⁴ _mVPP
Input Impedance
R_IN
(CLKIN_A+, CLKIN_A-, CLKIN_B+, CLKIN_B–,
REF/CLKIN_F+,
REF/CLKIN_F–)
—
80
—
kΩ
Differential Output Voltage Swing
(CLKOUT_[3:0])
V_OD
100 Ω Load
816 906 1100 _mVPP
Line-to-Line
Output Common Mode Voltage
(CLKOUT_[3:0])
V_OCM
100 Ω Load
1.4 1.8 2.2
V
Line-to-Line
Output Short to GND (CLKOUT_[3:0])
I_SC(–)
–60 —
—
mA
Output Short to V_DD25 (CLKOUT_[3:0])
I_SC(+)
— –45 —
mA
Input Voltage Low (LVTTL Inputs)
V_IL
—
—
0.8
V
Input Voltage High (LVTTL Inputs)
V_IH
2.0 —
—
V
Input Low Current (LVTTL Inputs)
I_IL
—
—
50
µA
Input High Current (LVTTL Inputs)
I_IH
—
—
50
µA
Input Impedance (LVTTL Inputs)
R_IN
50
—
—
kΩ
Internal Pulldown (LVTTL inputs)
I_pd
—
—
50
µA
FSYNC Output Charge Current
I_{OH_FSYNC} V_FSYNC = 0 V
100
—
—
µA
C_LOAD = 10 pF
FSYNC Output Discharge Current
I_{OL_FSYNC} V_FSYNC = V_DD
320
—
—
µA
C_LOAD = 10 pF
Notes:
1. The Si5364 device provides weak 1.5 V internal biasing that enables ac-coupled operation.
2. Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be ac-
coupled to ground.
3. Transmission line termination, when required, must be provided externally.
4. Although the Si5364 device can operate with input clock swings as high as 1500 mV_PP, Silicon Laboratories recommends
maintaining the input clock amplitude below 500 mV_PP for optimal performance.
Rev. 2.2
7