SI5364 Datasheet, PDF (16/40 Pages) Silicon Laboratories – SONET/SDH PRECISION PORT CARD CLOCK IC

Si5364
2. Functional Description
The Si5364 is a high-performance precision clock
switching and clock generation device. The Si5364
accepts up to three clock inputs in the 19 MHz range,
selects one of these clocks as the active clock input,
and generates up to four high-quality clock outputs that
are individually-programmable to be 1, 8, or 32x the
input clock frequency. Additional optional scaling by a
factor of 255/238 or 238/255 provides compatibility with
systems that provide or require clocks that are scaled
for forward error correction (FEC) rates. A typical
application for the Si5364 in SONET/SDH systems is
the generation of multiple low-jitter 19.44, 155.52, or
622.08 MHz clock outputs from a single or multiple
(redundant) 19.44 MHz reference clock sources.
The Si5364 employs Silicon Laboratories’ DSPLL
technology to provide excellent jitter performance,
minimize the external component count, and maximize
flexibility and ease of use. The Si5364’s DSPLL phase
locks to the selected clock input signal, attenuates
significant amounts of jitter, and multiplies the clock
frequency to generate the device’s SONET/SDH-
compatible clock outputs. The DSPLL loop bandwidth is
selectable, allowing the Si5364’s jitter performance to
be optimized for different applications. The Si5364 can
produce clock outputs with jitter generation as low as
0.30 ps_RMS (see Table 4 on page 10), making the
device an ideal solution for port card clocking in
SONET/SDH (including OC-48 and OC-192) and
Gigabit Ethernet systems.
Input clock selection and switching occurs manually or
automatically. Automatic switching is revertive or non-
revertive. The Si5364 monitors the clock input signals for
frequency accuracy and loss-of-signal and provides
frequency offset (FOS) and loss-of-signal (LOS) alarms
that are the basis for manual or automatic clock selection
decisions. Input clock switching in the Si5364 uses
Silicon Laboratories’ switching technology to minimize
the clock output phase transients normally associated
with clock rearrangement (switching). The resulting
Maximum Time Interval Error (MTIE) associated with
switching in the Si5364 is well below the limits specified
in Telcordia Technologies GR-1244-CORE for Stratum 2
and 3E clocks or Stratum 3 and 4E clocks.
The Si5364’s PLL utilizes Silicon Laboratories' DSPLL
technology to eliminate jitter, noise, and the need for
external loop filter components found in traditional PLL
implementations. A digital signal processing (DSP)
algorithm replaces the loop filter commonly found in
analog PLL designs. This algorithm processes the
phase detector error term and generates a digital
control value to adjust the frequency of the voltage-
controlled oscillator (VCO). The technology produces
low phase noise clocks with less jitter than is generated
using traditional methods. See Figure 6 for an example
phase noise plot. In addition, because external loop
filter components are not required, sensitive noise entry
points are eliminated, and the DSPLL is less susceptible
to board-level noise sources. Digital technology
provides highly-stable and consistent operation over all
process, temperature, and voltage variations. The
benefits are smaller, lower power, cleaner, more
reliable, and easier-to-use clock circuits.
2.0.1. Selectable Loop Filter Bandwidth
The digital nature of the DSPLL loop filter gives control
of the loop parameters without changing external
components. The Si5364 provides four selectable loop
bandwidth settings (800, 1600, 3200, or 6400 Hz) for
different system requirements. The loop bandwidth is
selected using the BWSEL[1:0] pins. The BWSEL[1:0]
settings and associated loop bandwidths are listed in
Table 7.
Table 7. Loop Bandwidth Settings
Loop Bandwidth
6400 Hz
3200 Hz
1600 Hz
800 Hz
BWSEL1 BWSEL0
1
1
0
0
0
1
1
0
Table 8. Nominal Clock Out Frequencies
Output Clock Frequency
622.08 MHz (32x multiplier)
155.52 MHz (8x multiplier)
19.44 MHz (1x multiplier)
Driver Powerdown
FSEL1
1
1
0
0
FSEL0
1
0
1
0
2.1. Clock Output Rate Selection
The Si5364’s DSPLL phase locks to the selected clock
input signal to generate an internal VCO frequency that
is a multiple of the input clock frequency. The internal
VCO frequency is divided down to produce four clock
outputs at 1, 8, or 32x the frequency of the clock input
signal. The clock rate for each clock output is selected
using the Frequency Select (FRQSEL[1:0]) pins
associated with that output. The FRQSEL[1:0] settings
and associated clock rates are listed in Table 8.
The input frequency ranges for the Si5364 are specified
in Table 3 on page 8. The output rates scale
accordingly. When a 19.44 MHz input clock is used, the
clock outputs are programmable to run at 19.44, 155.52,
or 622.08 MHz.
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Rev. 2.2