SI5364 Datasheet, PDF (19/40 Pages) Silicon Laboratories – SONET/SDH PRECISION PORT CARD CLOCK IC

Si5364
(t_{PT_MTIE}) is the steady-state offset between pre-
switching and post-switching output phases. This
specification applies to both the manual and automatic
switch modes. The clock output phase step slope (M_pt)
is defined as the rate of change of the output clock
phase during transition. Its magnitude depends on the
setting of the BWSEL[1:0] pins and whether the
switching is triggered manually by users or
automatically by Si5364 due to the changed input
clocks. The maximum transient phase deviation
(t_{PT_MTIE_MAX}) only applies to an automatic switch and
is defined as the maximum transient phase disturbance
on the output clock. This transient only occurs in the
automatic mode due to the delay between the actual
loss of the clock and when the LOS detection circuitry
detects the loss. During the delay, the phase detector
measures the phase change of the “lost” clock, and the
DSPLL moves the output clock’s phase accordingly.
When the LOS circuitry flags the loss of the clock,
Si5364 switches the reference to the alternate clock.
Since the internal phase monitor circuitry preserves the
phase difference before the event (loss of the original
clock), the output phase is restored, and no excessive
phase deviation is present.
Auto
m_PT
t_{PT_MTIE_MAX}
t_{PT_MTIE}
Loss of Clock
Manual
m_PT
t_{PT_MTIE}
2.5.2. Automatic Switching
The Si5364 provides automatic and manual control over
which input clock drives the DSPLL. Automatic
switching is selected when the AUTOSEL input is high.
Automatic switching is either revertive (return to the
default input after alarm conditions clear) or non-
revertive (remain with selected input until an alarm
condition exists on the selected input).
The prioritization of clock inputs for automatic switching
is CLKA, followed by CLKB, REF/CLKIN_F, and finally,
digital hold mode. Automatic switching mode defaults to
CLKIN_A at powerup, reset, or when in revertive mode
with no alarms present on CLKIN_A. If a LOS or FOS
alarm occurs on CLKIN_A and there are no active
alarms on CLKIN_B, the device switches to CLKIN_B. If
both CLKIN-A and CLKIN_B are alarmed and REF/
CLKIN_F is present and alarm-free, the device switches
to REF/CLKN_F. If no REF/CLKIN_F is present and
CLKIN_A and CLKIN_B are alarmed, the internal
oscillator digitally holds its last value. If automatic mode
is selected and DSBLFOS is active, automatic switching
is not initiated in response to FOS alarms.
2.5.3. Revertive/Non-Revertive Switching
In automatic switching mode, an alarm condition on the
selected input clock causes an automatic switch to the
highest priority non-alarmed input available. Automatic
switching is revertive or non-revertive, depending on the
state of the RVRT input. In revertive mode, if an alarm
condition on the currently-selected input clock causes a
switch to a lower priority input clock, the Si5364
switches to the original clock input when the alarm
condition is cleared. In revertive mode, the highest
priority reference source that is valid is selected as the
DSPLL input. In non-revertive mode, the current clock
selection remains as long as the selected clock is valid
even if alarms are cleared on a higher priority clock.
Figure 11 provides state diagrams for revertive mode
switching and for non-revertive mode switching.
Manual
Switch
Figure 10. Phase Transient Specification
Rev. 2.2
19