SI5364 Datasheet, PDF (32/40 Pages) Silicon Laboratories – SONET/SDH PRECISION PORT CARD CLOCK IC

Si5364
Pin #
Pin Name
Table 10. Pin Descriptions (Continued)
I/O
Signal Level
Description
H1
SYNCIN
I*
LVTTL
Synchronization Input for Frame Sync Clock.
Allows time alignment/realignment of the FSYNC
output clock. A rising edge on the SYNCIN input
forces alignment of the FSYNC output clock stream.
H2
DSBLFSYNC
I*
LVTTL
Disable the FSYNC Clock Output.
When high, the output driver for the FSYNC pin is
disabled.
A3
FEC[0]
I*
LVTTL
Forward Error Correction (FEC) Selection.
B3
FEC[1]
Enable or disable scaling of the input-to-output fre-
quency multiplication factor for FEC clock rate com-
patibility.
The multiplication ratios and associated frequency
ranges for the Si5364 clock outputs are set by the
FRQSEL pins associated with each clock output.
Additional scaling by a factor of either 255/238 or
238/255 can be applied to all active outputs as indi-
cated below.
The FEC[1:0] inputs are decoded as follows:
00 = No FEC scaling, FSYNC enabled.
01 = 255/238 FEC scaling for all clock outputs,
FSYNC disabled.
10 = 238/255 FEC scaling for all clock inputs,
FSYNC enabled.
11 = Reserved.
The FSYNC output is disabled when FEC[1:0] = 01.
A2
BWSEL[0]
I*
LVTTL
Bandwidth Select.
B2
BWSEL[1]
The BWSEL[1:0] pins set the bandwidth of the loop
filter within the DSPLL to 3200 Hz, 800 Hz, or
6400 Hz as indicated below.
00 = 3200 Hz
01 = 1600 Hz
10 = 800 Hz
11 = 6400 Hz
B10
CAL_ACTV
O
LVTTL
Calibration Mode Active.
Is driven high during the DSPLL self-calibration and
the subsequent initial lock acquisition period.
C7–9, D1–2, Rsvd_GND
—
F1–2
LVTTL
Reserved—Tie to Ground.
Must be tied to GND for normal operation.
B6–8, C6
Rsvd_NC
—
LVTTL
Reserved—No Connect.
Must be left unconnected for normal operation.
*Note: The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
low state if the input is not driven from an external source.
32
Rev. 2.2