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SI5364 Datasheet, PDF (11/40 Pages) Silicon Laboratories – SONET/SDH PRECISION PORT CARD CLOCK IC | |||
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Si5364
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ± 5%, TA = â20 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Jitter Transfer Bandwidth (see Figure 9)
Wander/Jitter Transfer Peaking
Wander/Jitter at 3200 Hz Bandwidth
(BWSEL[1:0] = 00)
Jitter Tolerance (see Figure 8)
FBW
JP
JTOL(PP)
BW = 1600 Hz
< 1600 Hz
â 1600 â Hz
â 0.0 0.1 dB
f = 32 Hz
f = 320 Hz
f = 3200 Hz
1000 â
100 â
10 â
â ns
â ns
â ns
CLKOUT RMS Jitter Generation
FEC[1:0] = 00 (1/1 Scaling)
JGEN(RMS)
12 kHz to 20 MHz
50 kHz to 80 MHz
â 0.89 1.2 ps
â 0.3 0.4 ps
CLKOUT RMS Jitter Generation
FEC[1:0] = 01, 10 (255/238, 238/255 Scal-
ing)
CLKOUT Peak-Peak Jitter Generation
FEC[1:0] = 00 (1/1 Scaling)
JGEN(RMS)
JGEN(PP)
12 kHz to 20 MHz
50 kHz to 80 MHz
12 kHz to 20 MHz
50 kHz to 80 MHz
â 0.81 1.2 ps
â 0.30 0.4 ps
â 5.8 10.0 ps
â 2.9 5.0 ps
CLKOUT Peak-Peak Jitter Generation
FEC[1:0] = 01, 10 (255/238, 238/255 Scal-
ing)
Jitter Transfer Bandwidth (see Figure 9)
Wander/Jitter Transfer Peaking
Wander/Jitter at 6400 Hz Bandwidth
(BWSEL[1:0] = 11)
Jitter Tolerance (see Figure 8)
JGEN(PP)
FBW
JP
JTOL(PP)
12 kHz to 20 MHz
50 kHz to 80 MHz
BW = 3200 Hz
< 3200 Hz
â 7.9 10.0 ps
â 4.6 5.0 ps
â 3200 â Hz
â 0.0 0.05 dB
f = 64 Hz
f = 640 Hz
1000 â
100 â
â ns
â ns
f = 6400 Hz
10 â â ns
CLKOUT RMS Jitter Generation
FEC[1:0] = 00 (1/1 Scaling)
JGEN(RMS)
12 kHz to 20 MHz
50 kHz to 80 MHz
â 1.03 1.4 ps
â 0.38 0.5 ps
CLKOUT RMS Jitter Generation
FEC[1:0] = 01, 10 (255/238, 238/255 scal-
ing)
CLKOUT Peak-Peak Jitter Generation
FEC[1:0] = 00 (1/1 Scaling)
JGEN(RMS)
JGEN(PP)
12 kHz to 20 MHz
50 kHz to 80 MHz
12 kHz to 20 MHz
50 kHz to 80 MHz
â 1.01 1.4 ps
â 0.45 0.6 ps
â 9.3 12.0 ps
â 2.8 5.5 ps
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude
for the Si5364 (tPT_MTIE) never reaches one nanosecond.
Rev. 2.2
11
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