SI5364 Datasheet, PDF (1/40 Pages) Silicon Laboratories – SONET/SDH PRECISION PORT CARD CLOCK IC

Si5364
SONET/SDH PRECISION PORT CARD CLOCK IC
Features
Ultra-low jitter clock outputs with jitter
generation as low as 0.3 ps_RMS
No external components (other than a
resistor and standard bypassing)
Up to three clock inputs
Four independent clock outputs at 19,
155, or 622 MHz
Stratum 3, 3E, and SMC compatible
Digital hold for loss-of-input clock
Applications
SONET/SDH line/port cards
Terabit routers
Automatic or manually-controlled hitless
switching between clock inputs
Revertive/non-revertive switching
Loss-of-signal and frequency offset
alarms for each clock input
Support for forward and reverse FEC
clock scaling
8 kHz frame sync output
Low power
Small size (11x11 mm)
Core switches
Digital cross connects
Si5364
Bottom View
Ordering Information:
See page 36.
Description
The Si5364 is a complete solution for ultra-low jitter high-speed clock generation and
distribution in precision clocking applications, such as OC-192/OC-48 SONET/SDH line/
port cards. This device phase locks to one of three reference inputs in the range of
19.44 MHz and generates four synchronous clock outputs that can be independently
configured for operation in the 19, 155, or 622 MHz range (1, 8, and 32x input clock).
Silicon Laboratories DSPLL™ technology delivers phase-locked loop (PLL) functionality
with unparalleled performance while eliminating external loop filter components,
providing programmable loop parameters, and simplifying design. The on-chip reference
monitoring and clock switching functions support Stratum 3/3E and SMC compatible
clock switching with excellent output phase transient characteristics. FEC rates are
supported with selectable 255/238 or 238/255 scaling of the clock multiplication ratios.
The Si5364 establishes a new standard in performance and integration for ultra-low jitter
clock generation. It operates from a single 3.3 V supply.
Functional Block Diagram
REXT
VSEL33 VDD
GND
FEC[1:0]
BWSEL[1:0]
CLKIN_A+
2
CLKIN_A–
CLKIN_B+
2
CLKIN_B–
REF/CLKIN_F+
2
REF/CLKIN_F–
LOS_A
FOS_A
LOS_B
FOS_B
LOS_F
DSBLFOS
SMC/S3N
VALTIME
AUTOSEL
RVRT
MANCNTRL[1:0]
INCDELAY
DECDELAY
FXDDELAY
A_ACTV
B_ACTV
Biasing & Supply
2
2
SiLECT^TM
Switching
DSPLL^TM
Signal
Detection,
Selection,
& Control
DH_ACTV
F_ACTV
RSTN/CAL
CAL_ACTV
CLKOUT_1+
÷
CLKOUT_1–
2
FRQSEL_1[1:0]
÷
CLKOUT_2+
CLKOUT_2–
2
FRQSEL_2[1:0]
÷
CLKOUT_3+
CLKOUT_3–
2
FRQSEL_3[1:0]
CLKOUT_4+
÷
CLKOUT_4–
2
FRQSEL_4[1:0]
÷
FSYNC
DSBLFSYNC
SYNCIN
Rev. 2.2 7/04
Copyright © 2004 by Silicon Laboratories
Si5364