SI5364 Datasheet, PDF (31/40 Pages) Silicon Laboratories – SONET/SDH PRECISION PORT CARD CLOCK IC

Si5364
Pin #
Pin Name
Table 10. Pin Descriptions (Continued)
I/O
Signal Level
Description
K4
CLKOUT_1+
O
K3
CLKOUT_1–
CML
Differential Clock Output 1.
High-frequency output clock derived from the
selected reference source (CLKIN_A, CLKIN_B, or
REF/CLKIN_F) or from Digital hold mode.
The frequencies of the Si5364 clock outputs are
each 1, 8, or 32x multiple of the frequency of the
selected clock input. The multiplication ratio is
selected using Frequency Select (FRQSEL) control
pins associated with each clock output. An additional
scaling factor of either 238/255 or 255/238 can be
selected for FEC operation using the FEC[1:0] con-
trol pins.
K6
CLKOUT_2+
O
K7
CLKOUT_2–
CML
Differential Clock Output 2.
See CLKOUT_1.
K10
CLKOUT_3+
O
K9
CLKOUT_3–
CML
Differential Clock Output 3.
See CLKOUT_1.
H10
CLKOUT_4+
O
G10
CLKOUT_4–
CML
Clock Output 4.
See CLKOUT_1.
J3
FRQSEL_1[0]
I*
J4
FRQSEL_1[1]
LVTTL
Frequency Select—Clock Out 1.
Selects the multiplication factor between the fre-
quency of the selected clock input and the frequency
of the clock output.
The FRQSEL_1[1:0] inputs are decoded as follows:
00 = Clock Driver Power Down.
01 = 1x multiplication (19.44 MHz output typical).
10 = 8x multiplication (155.52 MHz output typical).
11 = 32x multiplication (622.08 MHz output typical.
The clock output multiplication ratios can be scaled
additionally by a factor of 255/238 or 238/255 for
FEC operation. See FEC[1:0] pin description.
J6
FRQSEL_2[0]
I*
J7
FRQSEL_2[1]
LVTTL
Frequency Select—Clock Out 2.
See FRQSEL_1[1:0].
J10
FRQSEL_3[0]
I*
J9
FRQSEL_3[1]
LVTTL
Frequency Select—Clock Out 3.
See FRQSEL_1[1:0].
G9
FRQSEL_4[0]
I*
H9
FRQSEL_4[1]
LVTTL
Frequency Select—Clock Out 4.
See FRQSEL_1[1:0].
J1
FSYNC
O
See Table 3 Frame Sync Clock.
Nominally 8 kHz based on a 19.44 MHz reference.
The 8 kHz frame sync is disabled when 255/238 FEC
scaling of the clock output frequencies is selected.
See FEC[1:0] pin description.
*Note: The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
low state if the input is not driven from an external source.
Rev. 2.2
31