SI5364 Datasheet, PDF (12/40 Pages) Silicon Laboratories – SONET/SDH PRECISION PORT CARD CLOCK IC

Si5364
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(V_DD33 = 3.3 V ± 5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
CLKOUT Peak-Peak Jitter Generation
FEC[1:0] = 01, 10 (255/238, 238/255 scal-
ing)
Jitter Transfer Bandwidth (see Figure 9)
Wander/Jitter Transfer Peaking
Acquisition Time
Clock Output Wander with
Temperature Gradient ^1,2
Initial Frequency Accuracy in Digital Hold
Mode (first 100 ms with supply voltage and
temperature held constant)
Clock Output Frequency Accuracy Over
Temperature in Digital Hold Mode
Clock Output Frequency Accuracy Over
Supply Voltage in Digital Hold Mode
Clock Output Phase Step
Clock Output Phase Step Slope³â€”Manual
Switches
BWSEL[1:0] = 11
BWSEL[1:0] = 00
BWSEL[1:0] = 01
BWSEL[1:0] = 10
J_GEN(PP)
12 kHz to 20 MHz
50 kHz to 80 MHz
— 7.1 12.0 ps
— 3.0 5.5 ps
F_BW
BW = 6400 Hz
— 6400 — Hz
J_P
< 6400 Hz
— 0.05 .1 dB
T_AQ
RSTN/CAL high to
— 195 350 ms
CAL_ACTV low, with valid
clock input and VALTIME = 0
C_{CO_TG}
Stable Input Clock;
Temperature
Gradient < 10 °C/min;
800 Hz Loop BW
— — 40 ps/
°C/
min
C_{DH_FA}
Stable Input Clock
Selected until entering
Digital Hold
— — 7.0 ppm
C_{DH_T}
C_{DH_V33}
Constant Supply Voltage
Constant Temperature
— 16.2 30 ppm
/°C
— 25 500 ppm
/V
t_{PT_MTIE}
m_PT
During Clock Switching
1/1
During Clock Switching
–200 0
200 ps
6400 Hz
3,200 Hz
1600 Hz
800 Hz
— — 10 ps/
— — 5 µs
— — 2.5
— — 1.25
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude
for the Si5364 (t_{PT_MTIE}) never reaches one nanosecond.
12
Rev. 2.2