SI5364 Datasheet, PDF (17/40 Pages) Silicon Laboratories – SONET/SDH PRECISION PORT CARD CLOCK IC

Si5364
2.1.1. FEC Rate Conversion
Conversion from non-FEC to FEC rates and from FEC
to non-FEC rates is supported with selectable 238/255
or 255/238 scaling of the Si5364’s clock output
multiplication ratios.
The multiplication ratios and associated frequency
ranges for the Si5364 clock outputs are set by the
FRQSEL[1:0] pins associated with each clock output.
Additional frequency scaling of active clock outputs by a
factor of either 238/255 or 255/238 is selected using the
FEC[1:0] control inputs.
For example, a 622.08 MHz output clock (a non-FEC
rate) is generated from a 19.44 MHz input clock (a non-
FEC rate) by setting FRQSEL[1:0] = 11 (32x
multiplication) and setting FEC[1:0] = 00 (no FEC
scaling). A 666.51 MHz output clock (a FEC rate) is
generated from a 19.44 MHz input clock (a non-FEC
rate) by setting FRQSEL[1:0] = 11 (32x multiplication)
and setting FEC[1:0] = 01 (255/238 FEC scaling).
Finally, a 622.08 MHz output clock (a non-FEC rate) is
generated from a 20.83 MHz input clock (a FEC rate) by
setting FRQSEL [1:0] = 11 (32x multiplication) and
setting FEC[1:0] = 10 (238/255 FEC scaling). The
FEC[1:0] settings and associated scaling factors are
listed in Table 9.
Table 9. FEC Rate Conversion
FEC Frequency FEC1
Scaling
FEC0 FSYNC
1/1
0
0
Enabled
255/238
0
1
Disabled
238/255
1
0
Enabled
Reserved
1
1
2.2. PLL Performance
The Si5364 PLL provides extremely low jitter
generation, high jitter tolerance, and a well-controlled
jitter transfer function with low peaking and a high
degree of jitter attenuation. Each of these key
performance parameters is described in the following
sections.
2.2.1. Jitter Tolerance
Jitter tolerance for the Si5364 is defined as the
maximum peak-to-peak sinusoidal jitter that can be
present on the incoming clock. Tolerance is a function of
the input jitter frequency and improves for lower input
jitter frequency.
Input
Jitter
A m p litu d e
–20 dB/dec.
10 ns
Excessive Input Jitter Range
F_BW
f_{Jitter In}
Figure 8. Jitter Tolerance Mask/Template
Jitter
Transfer
Jitter Out
Jitter In
(s
)
0 dB
Peaking
–20 dB/dec.
F_BW
f_Jitter
Figure 9. PLL Jitter Transfer Mask/Template
2.2.2. Jitter Transfer
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of
input clock jitter that passes to the outputs. The DSPLL
technology used in the Si5364 provides tightly
controlled jitter transfer curves because the PLL gain
parameters are determined by digital circuits that do not
vary over supply voltage, process, and temperature. In
a system application, a well-controlled transfer curve
minimizes the output clock jitter variation from board to
board for consistent system-level jitter performance.
The jitter transfer characteristic is a function of the
BWSEL[1:0] setting. Lower bandwidth selection results
in more jitter attenuation of the incoming clock but might
result in higher jitter generation. Table 4 on page 10
gives the 3 dB bandwidth and peaking values for
specified BWSEL[1:0] settings. Figure 9 shows the jitter
transfer curve mask.
2.2.3. Jitter Generation
Jitter generation is defined as the amount of jitter
produced at the output of the device with a jitter-free
input clock. Jitter is generated from sources within the
VCO and other PLL components. Jitter generation is a
function of the PLL bandwidth setting.
Rev. 2.2
17