SI5364 Datasheet, PDF (26/40 Pages) Silicon Laboratories – SONET/SDH PRECISION PORT CARD CLOCK IC

Si5364
Pin #
Pin Name
Table 10. Pin Descriptions
I/O
Signal Level
Description
C2
CLKIN_A+
I*
AC Coupled System Clock Input A.
C1
CLKIN_A–
200–500 mV_{PPD One of three differential clock inputs selected by the}
(See Table 2) _{DSPLL when generating the SONET/SDH compliant}
clock outputs. The frequencies of the Si5364 clock
outputs are each a 1, 8, or 32x multiple of the fre-
quency of the selected clock input. The multiplication
ratio is selected using Frequency Select (FRQSEL)
control pins associated with each clock output. An
additional scaling factor of either 238/255 or 255/238
is selected for FEC operation using the FEC[1:0]
control pins.
The clock input frequency is nominally 19.44 MHz.
The clock input frequency can be varied over the
range indicated in Table 3 on page 8 to produce
other output frequencies.
CLKIN_A is the highest priority clock input during
automatic switching mode operation.
G1
CLKIN_B+
I*
AC Coupled System Clock Input B.
G2
CLKIN_B–
200–500 mV_{PPD One of three differential clock inputs selected by the}
(See Table 2) _{DSPLL when generating the SONET/SDH compliant}
clock outputs. The frequencies of the Si5364 clock
outputs are each a 1, 8, or 32x multiple of the fre-
quency of the selected clock input. The multiplication
ratio is selected using Frequency Select (FRQSEL)
control pins associated with each clock output. An
additional scaling factor of either 238/255 or 255/238
can be selected for FEC operation using the
FEC[1:0] control pins.
The clock input frequency is nominally 19.44 MHz.
and can be varied over the range indicated in Table 3
on page 8 to produce other output frequencies.
CLKIN_B is the second highest priority clock input
during automatic switching mode operation.
*Note: The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
low state if the input is not driven from an external source.
26
Rev. 2.2