SI5364 Datasheet, PDF (35/40 Pages) Silicon Laboratories – SONET/SDH PRECISION PORT CARD CLOCK IC

Si5364
Pin #
Pin Name
Table 10. Pin Descriptions (Continued)
I/O
Signal Level
Description
C5
FXDDELAY
I*
LVTTL
Fixed Delay Control.
Active high input that fixes the clock input to clock
output phase relationship to a constant value. When
this pin is high and the device is operating in manual
select mode (AUTOSEL = 0), hitless recovery from
digital hold is disabled, and the input to output phase
relationship will remain fixed as long as the
MANCNTRL[1:0] pins remain unchanged.
This feature is useful in applications that utilize a
single clock source and require a known input-to-
output phase relationship. The FXDDELAY input is
ignored when AUTOSEL is high.
*Note: The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
low state if the input is not driven from an external source.
Rev. 2.2
35